Skip to main content
Log in

DPLLs in Wireless Communication: Current State and Trends—A Literature Survey

  • Review Paper
  • Published:
Journal of The Institution of Engineers (India): Series B Aims and scope Submit manuscript

Abstract

Communication technologies have seen massive growth over the past few decades. Though advanced features provided by contemporary 3G and 4G systems lead to increased popularity among masses`, providing satisfactory services remain an issue with user number and applications growing exponentially. Replacement approaches have already been devised including the testing of fifth-generation systems which promises to meet the ever-increasing demands of higher data rates with low latency and uniform coverage with decreasing constraints related to power and quality of service. In this scenario, phase-locked loop (PLL) receivers in many forms have started to receive greater attention. Since its first successful use in 1932, PLLs in varied incarnations including digital PLL (DPLL) have been accepted to be integral elements of communication setups. One of the major advantages of DPLL is its ability to ensure error minimization using a phase-dependent approach at the cost of increase in computational latency. A new class of designs has recently emphasized on minimizing the time delay in DPLL loop using different techniques to achieve time-efficient symbol recovery by parallelizing loop actions. Similarly, clustering techniques could be efficiently used for this purpose. A detailed survey on different aspects related to design of low latency DPLLs with acceptable error rates is presented here.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Q. Nasir, S. Al-Araji, Linearized phase detector zero crossing DPLL performance evaluation in faded mobile channels. Int. J. Circ. Syst. 2(3), 139–144 (2011). https://doi.org/10.4236/cs2011.23021

    Article  Google Scholar 

  2. Rohde and Schwarz, 5G technology (2014). www.rohdeschwarz.com/en/solutions/wireless-communications/5g/5g-fundamentals/5g-fundamentals_229439.html/. Accessed Sept 2015

  3. B.B. Purkayastha, K.K. Sarma, A digital phase-locked loop based signal and symbol recovery system for wireless channel. Dissertation, Department of Electronics and Communication Technology, University of Gauhati (2012)

  4. B.B. Purkayastha, K.K. Sarma, A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel. Signals and Communication Technology (Springer, New Delhi, 2015)

    Google Scholar 

  5. E. Salahat, M.A. Qutayri, S.R. Al-Araji, H. Saleh, A zero crossing digital phase locked loop architecture with hyperbolic nonlinearity for high doppler environments, in Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, Marseille (2014), pp. 56–59

  6. E. Salahat, M.A. Qutayri, S.R. Al-Araji, Robust hyperbolic sigma delta based no delay tan lock loop for wireless communications, in Proceedings of the 80th IEEE Vehicular Technology Conference(VTC Fall), Vancouver BC, (2014), pp. 1–4

  7. J. Lee, C. Un, Performance analysis of digital tanlock loop. IEEE Trans. Commun. 30, 2398–2411 (1982)

    Article  Google Scholar 

  8. Z.M. Hussain, B. Boashash, M. Hassan-Ali, S.R. Al-Araji, A time-delay digital tanlock loop. IEEE Trans. Signal Process. 49, 1808–1815 (2001)

    Article  Google Scholar 

  9. M.A. Al-Qutayri, S.R. Al-Araji, O.A. Al-Ali, N.A. Anani, Adaptive digital tanlock loop with no delay, in Proceedings of the IEEE Conference on Electronics, Circuits, and Systems, Beirut (2011), pp. 73–76

  10. G. Eynard, C. Laot, Extended linear phase detector characteristics of a software PLL, in Proceedings of the 3rd International Symposium on Communications, Control and Signal Processing, St. Julians (2008), pp. 62–67

  11. B. Farhang-Boroujeny, Signal processing techniques for software radio (2007). www2.elen.utah.edu/farhang. Accessed 25 Sept 2015

  12. M. Oerder, H. Meyr, Digital filter and square timing recovery. IEEE Trans. Commun. 36, 605–612 (1988)

    Article  Google Scholar 

  13. A. Montazeri, K. Kiasaleh, Design and performance analysis of a low complexity digital clock recovery algorithm for software defined radio applications. IEEE Trans. Consum. Electron. 56(3), 1258–1263 (2010)

    Article  Google Scholar 

  14. J. Zhang, A novel symbol synchronization method for OFDM systems in SFN channels. IEEE Trans. Consum. Electron. 54, 1550–1554 (2008)

    Article  Google Scholar 

  15. L. Huang, L. Pingfen, A new lock detector for Gardner’s timing recovery method. IEEE Trans. Consum. Electron. 54, 349–352 (2008)

    Article  Google Scholar 

  16. E. Salahat, S.R. Al-Araji, M. Al-Qutayri, A frequency synthesizer based on zero crossing digital phase locked loop, in Proceedings of the 20th IEEE International Conference on Electronics, Circuits and Systems, Abu Dhabi, December (2013), pp. 835–838

  17. D. Ye, P. Lu, P. Andreani, R.A. Zee, wide bandwidth Fractional-N synthesizer for LTE with phase noise cancellation using a hybrid delta-sigma DAC and charge re-timing, in Proceedings of the IEEE International Symposium on Circuits and Systems, Beijing, May (2013)

  18. S.R. Al-Araji, E. Salahat, D. Kilani, S.A. Yasin, H. Alkhoja, J. Aweya, Adaptive zero crossing digital phase locked loop for packet synchronization, in Proceedings of the 11th IEEE International New Circuits and Systems Conference, Paris, June (2013), pp. 1–4

  19. S. Kandeepan, Steady state distribution of a hyperbolic digital tanlock loop with extended pull-in range for frequency synchronization in high doppler environment. IEEE Trans. Wirel. Commun. 8(2), 890–897 (2009)

    Article  Google Scholar 

  20. S. Levantino, Advanced digital phase locked loops, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose CA, September (2013), pp. 1–95

  21. C.M. Hsu, M.Z. Straayer, M.H. Perrott, A low-noise, wide-BW 3.6 GHz digital Fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation, in Proceedings of the IEEE International Conference on Solid State Circuits, San Fransisco CA, February (2008), pp. 340–341

  22. C. Weltin-Wu, E. Temporiti, D. Baldi, F. Svelto, A 3 GHz Fractional-N all-digital PLL with precise time-to-digital converter: calibration and mismatch correction, in Proceedings of the IEEE International Conference on Solid State Circuits, San Fransisco CA, February, pp. 344–345 (2008)

  23. A. Rylyakov et al., Bang Bang Digital PLLs at 11 and 20 GHz with sub-200 fs integrated jitter for high speed serial communication applications, in Proceedings of the IEEE International Solid State Circuits Conference, San Fransisco CA, February (2009), pp. 94–95

  24. S. Levantino, C. Samori, Non-linearity cancellation in digital PLLs, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose CA, September (2013), pp. 1–8

  25. R.B. Staszewski, J.L. Wallberg, S. Rezeq et al., All-digital PLL and transmitter for mobile phones. IEEE J. Solid State Circ. 40(12), 2469–2482 (2005)

    Article  Google Scholar 

  26. M. Hekmat et al., A 25 GHz fast-lock digital LC PLL with multiphase output using a magnetically-coupled loop of oscillators. IEEE J. Solid State Circ. 50(2), 490–502 (2015)

    Article  Google Scholar 

  27. C.C. Hung, S.I. Liu, A 40-GHz fast-locked all-digital phase locked loop using a modified bang-bang algorithm. IEEE Trans. Circ. Syst. 58(6), 321–325 (2011)

    Google Scholar 

  28. R.B. Staszewski, P.T. Balsara, All-digital PLL with ultra fast settling. IEEE Trans. Circ. Syst. 54(2), 181–185 (2007)

    Article  Google Scholar 

  29. R.B. Staszewski, G. Shriki, P.T. Balsara, All-digital PLL with ultra fast acquisition, in Proceedings of the IEEE Asian Solid-State Circuits Conference, Hsinchu, November (2005), pp. 289–292

  30. C.C. Hung, S.I. Liu, A 35.56 GHz all-digital phase-locked loop with high resolution varactors, in Proceedings of the International Symposium on VLSI Design Automation and Test, Hsinchu, Taiwan, April (2010), pp. 245–248

  31. P. Gianni, A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems, in Proceedings of the IEEE Seventh International Southern Conference on Programmable Logic, Corodoba, April (2011), pp. 31–36

  32. M. Kuschnerov et al., DSP for coherent single carrier receivers. J. Light Technol. 27(16), 3614–3622 (2009)

    Article  Google Scholar 

  33. P. Gianni et al., A new parallel carrier recovery architecture for intradyne coherent optical receivers in the presence of laser frequency fluctuations, in Proceedings of the IEEE Global Communications Conference, Houston, Texas, USA (2011), pp. 1–6

  34. E. Ip, J. Kahn, Feedforward carrier recovery for coherent optical communications. J. Light Technol. 25(9), 2675–2692 (2007)

    Article  Google Scholar 

  35. M. Azuma, H. Hikawa, Supervised learning of DPLL based winner-take-all neural network, in Proceedings of the IEEE International Conference on Evolvable Systems, Orlando, Florida, December (2014), pp. 117–124

  36. K. Yasuaki, Spiking neural networks: learning methods and related topics. Int. J. Syst. Control Inf. 48(2), 57–62 (2015)

    Google Scholar 

  37. C.H. Shan et al., An all digital phase locked loop system with high performance on wideband frequency tracking, in Proceedings of the Ninth International Conference on Hybrid Intelligent Systems, Shenyang (2009), pp. 460–463

  38. L. Su-gang, Y. Zhi-jia, An improved all digital phase-locked loop design. Int. J. Microcomput. Inf. 21(25), 42–43 (2005)

    Google Scholar 

  39. C.L. Lu et al., A parallel carrier synchronization algorithm for high speed digital communication systems, in Proceedings of the 6th International Conference on Wireless Communications Networking and Mobile Computing, Chengdu, September (2010), pp. 1–4

  40. L. Rakotondrainibe, Y. Kokar, G. Zaharia, 60 GHz high data rate wireless communication system, in Proceedings of the IEEE 69th Vehicular Technology Conference, Barcelona, April (2009), pp. 1–5

  41. W. Namgoong, Observer-controller digital PLL. IEEE Trans. Circ. Syst. 57(3), 631–641 (2010)

    MathSciNet  Google Scholar 

  42. M. Lee, A. Abidi, A 9b, 1.25 ps resolution coarse-fine time-to digital converter in 90 nm CMOS that amplifies a time residue. IEEE J. Solid State Circ. 43(4), 769–777 (2008)

    Article  Google Scholar 

  43. M.F. Wagdy, A novel flash fast locking digital phase locked loop, in Proceedings of the Sixth International Conference on Information Technology: New Generations, Las Vegas, April (2009), pp. 47–52

  44. O. Al-Kharji Ali et al., Digital tanlock loop without a phase shifter, in Proceedings of the 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, Manchester, December (2014), pp. 851–855

  45. C. Shan, All DPLLs based on fuzzy PI control algorithm, in Proceedings of the Second IEEE International Mechanic Automation and Control Engineering, Hohot, July (2011), pp. 7150–7153

  46. A. Mandal et al., Implementation of coordinate rotation algorithm for digital phase locked loop system in in-phase and quadrature phase signal processing, in Proceedings of the Third International Conference on Emerging Trends in Engineering and Technology, Goa, November (2010), pp. 721–725

  47. A. Mandal, K.C. Tyagi, B.K. Kaushik, VLSI Architecture design and implementation for application specific CORDIC processor, in Proceedings of the 2nd International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, October (2010), pp. 775–762

  48. M. Li et al., A C-programmable baseband processor with inner MODEM implementations for LTE CAT4/5/7 and GBPS 80 MHz 4 × 4 802.11AC, in Proceedings of the Global Conference on Signal and Information Processing, Austin, December (2013), pp. 1222–1225

  49. D. Liu, A. Nilsson, E. Tell, D. Wu, J. Eilert, Bridging dream and reality: programmable baseband processors for software-defined radio. IEEE Commun. Mag. 47(9), 134–140 (2009)

    Article  Google Scholar 

  50. Y. Jin et al., An intelligent task allocation scheme for multihop wireless networks. IEEE Trans. Parallel Distrib. Syst. 23(3), 444–451 (2012)

    Article  Google Scholar 

  51. V. Tsiatsis, R. Kumar, M.B. Srivastava, Computation hierarchy for in-network processing. Int. J. Mob. Netw. Appl. 10(4), 505–518 (2005)

    Article  Google Scholar 

  52. E. Kijsiongse, S. U-ruekelon, Dynamic load balancing on GPU clusters for large-scale K-means clustering, in Proceedings of the Ninth International Joint Conference on Computer Science and Software Engineering, Bangkok, May–June (2012), pp. 346–350

  53. G. Mani et al., Balanced block design architecture for parallel computing in mobile CPUs/GPUs, in Proceedings of the Fourth International Conference on Computing for Geospatial Research and Application, San Jose CA, July (2013), pp. 140–141

  54. G. Mani, S. Berkovich, I. Mihai, A combinatorial distributed architecture for exascale computing, in Proceedings of the Fourth IEEE International Conference on Advanced Computing, Chennai, December (2012), pp. 1–5

  55. X. Ling et al., Fast and efficient parallel-shift water-filling algorithm for power allocation in orthogonal frequency division multiplexing-based underlay cognitive radios. IET Commun. 7(12), 1269–1278 (2012)

    Article  Google Scholar 

  56. X. Gong, S.A. Vorobyov, C. Tellambura, Optimal bandwidth and power allocation for sum ergodic capacity under fading channels in cognitive radio networks. IEEE Trans. Signal Process. 59(4), 1814–1826 (2011)

    Article  MathSciNet  Google Scholar 

  57. K. Sonet et al., Power allocation for OFDM-based cognitive radio systems under outage constraint, in Proceedings of the IEEE International Conference on Communications, Cape Town, South Africa, May (2010), pp. 1–5

  58. D.R. Palormar, J.R. Fonollosa, Practical algorithm for a family of waterfilling solutions. IEEE Trans. Signal Process. 53(2), 686–695 (2005)

    Article  MathSciNet  Google Scholar 

  59. B.R. Nanjesh, MPI based cluster computing for performance evaluation of parallel applications, in Proceedings of the IEEE International Conference on Information and Communication Technologies, JeJu Island, April (2013), pp. 1123–1128

  60. A. Radenski, Shared memory, message passing, and hybrid merge sorts for standalone and clustered SMPs, in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, San Jose, November (2011), pp. 367–373

  61. W. Gropp, Recent advances in parallel virtual machine and message passing interface, in MPICH2: A New Start for MPI Implementations. Lecture Notes in Computer Science, vol. 2474 (Springer, Heidelberg, 2002), pp. 7–7

  62. H.R. Myler, A concurrent processing approach for software defined radio baseband design, in Proceedings of the IEEE Region 5 and IEEE Denevar Section Technical, Professional and Student Development Workshop (Software Define Radio Laboratory, Dept. of Electrical Engineering, University of Lamar, Beamount, Texas, 2005), pp. 24–28

  63. P. Lee, Has FPGA technology peaked in wideband wireless applications. IEEE Radio Commun. 42, S4–S5 (2004)

    Google Scholar 

  64. N. Abughalieh et al., Adaptive parallel concatenation turbo codes for wireless sensor networks, in Proceedings of the International Conference on Communications and Information Technology, Aqaba (2011), pp. 180–183

  65. N. Abughalieh, K. Steenhaut, A. Nowe, Low power channel coding for wireless sensor networks, in Proceedings of the Seventeenth Annual Symposium of the IEEE/CVT Benelux Chapter, Enschede, November (2010), pp. 1–5

  66. S.L. Howard, C. Schlegel, K. Iniewski, Error control coding in low-power wireless sensor networks: when is ECC energy-efficient. Eur. Assoc. Signal Process. J. Wirel. Commun. Netw. 2006, 1–14 (2006). https://doi.org/10.1155/WCN/2006/74812

    Article  Google Scholar 

  67. Zigbee Alliance. Learn about Zigbee (2011). http://www.zigbee.org/. Accessed Sept 2015

  68. Silicon Team, All digital PLL application (2012). https://www.silabs.com/applications/communicationstelecom/Pages/All-Digital-PLL.aspx/. Accessed Aug 2015

  69. Silicon Team, Crystal oscillator devices, XO (2010). https://www.silabs.com/products/clocksoscillators/xo/Pages/default.aspx/. Accessed Aug 2015

  70. Wireless Communications Business Unit, SWRA 029: Fractional/Integer-N PLL Basics (1999). http://www.ti.com/lit/an/swra029/swra029.pdf. Accessed Aug 2015

  71. Microsemi Team, Digital PLL ZC30100/1/9 (2004). http://www.microsemi.com/document-portal/doc_view/127421-zl30100-1-product-preview-oct2004/. Accessed Nov 2015

  72. IBM Research Center Team, Digital phase locked loop (2012). http://researcher.watson.ibm.com/researcher/view_group.php?id=1050, Accessed Oct 2015

  73. Qualcomm Team, Qualcomm snapdragon (2014). https://www.qualcomm.com/products/snapdragon/processors/810. Accessed Oct 2015

  74. Amazon and Tescun Team, Tescun PL-505-Digital Portable Shortwave (2011). http://www.amazon.com/Tecsun-PL-505-Digital-Portable-Shortwave/dp/B00669VXHS, Accessed Oct 2015

  75. Amazon and Tescun Team, Tescun PL-360-Digital Portable Shortwave (2011). http://www.amazon.com/Tecsun-PL-360-Digital-Portable-Shortwave/product-reviews/B004QJKO52. Accessed Oct 2015

  76. Amazon and Tescun Team, Tescun BCL-3000 Digital Portable Shortwave. http://www.amazon.com/BCL-3000-BCL3000-Receiver-Display-Portable/dp/B00NFAZCRS, Accessed Oct 2015 (2011)

  77. S. Bhattacharyya, R.N. Ahmed, B.B. Purkayastha, K. Bhattacharyya, Zero crossing algorithm based phase recovery for DPLL based wireless communication, in Proceedings of the IEEE International Conference on Computing, Communication and Automation, School of Computing Science and Engineering, Galgotias University, Greater Noida, India, May (2015), pp. 1220–1226

  78. S. Bhattacharyya, A. Misra, K.K. Sarma, A modified LSPF-DPLL based phase resolver for wireless communication, in Proceedings of the 3rd IEEE International Conference on Recent Advances in Information Technology, Dhanbad, India, March (2016), pp. 65–71

  79. Mathworks, BER performance of different equalizers. Internet: http://in.mathworks.com/help/comm/examples/ber-performance-of-different-equalizers.html. 25 Oct 2011 [3 Feb 2016]

  80. S. Bhattacharyya, A. Misra, K.K. Sarma, A BCH code assisted modified LSPF-DPLL topology for Nakagami-m, Rayleigh and Rician fading channels. Accepted Manuscript to appear in the Els. Int. J. Digit. Commun. Netw. (2017). https://doi.org/10.1016/j.dcan.2017.10.001

    Article  Google Scholar 

  81. S. Bhattacharyya, A. Misra, K.K. Sarma, A parallelized phase-frequency detector based modified LSPF-DPLL for wireless communication, in Proceedings of the 20th International Conference on Circuits, Systems, Communications and Computers (CSCC 2016), Corfu Island, Greece, July (2016), pp. 1–8

  82. M. Peng, S. Yan, K. Zhang, C. Wang, Fog computing based radio access networks: issues and challenges. IEEE Netw. 30(4), 46–53 (2016)

    Article  Google Scholar 

  83. M. Peng, Y. Li, Z. Zhao, C. Wang, System Architecture and key technologies for 5G heterogenous cloud radio access networks. IEEE Netw. 29(2), 6–14 (2015)

    Article  Google Scholar 

Download references

Acknowledgements

We would like to extend our gratitude to Mr. Basab Bijoy Purkayastha, Dept. of Physics, Indian Institute of Technology, Guwahati, and Mr. Kaustubh Bhattacharyya, Dept. of ECE, School of Technology, Assam, and Don Bosco University, for their valuable suggestions provided during the survey. The authors are also grateful to the Ministry of Communication and Information Technology, Govt. of India, for facilitating the research.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Sabyasachi Bhattacharyya.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bhattacharyya, S., Misra, A. & Sarma, K.K. DPLLs in Wireless Communication: Current State and Trends—A Literature Survey. J. Inst. Eng. India Ser. B 100, 627–647 (2019). https://doi.org/10.1007/s40031-019-00412-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s40031-019-00412-0

Keywords

Navigation