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A Precise Implementation of Random Access Time Measurement for Embedded SRAM

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Abstract

With the development of semiconductor process technology and circuit design capabilities, operating frequency of random access memory has been improved dramatically. Accurate measurement of embedded memory random access time is becoming a challenge, especially for low-density embedded memory. Traditional timing measurement which connects the external ports directly to the internal ports of memory is not feasible for its low efficiency and very low precision. A new method which applied the built-in test circuit to memory access timing measurement is presented in this paper. With high-speed static random access memory testing chip fabricated with 28 nm logic process, the proposed access timing measurement circuit has been verified and proved to be accurate.

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Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 61272105 and 61076102).

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Authors and Affiliations

  1. School of Urban Rail Transportation, Soochow University, Suzhou, 215006, People’s Republic of China

    L. J. Zhang, Y. F. Zhang, Y. Z. Li & L. F. Mao

  2. School of Electronic and Information Engineering, Soochow University, Suzhou, 215006, People’s Republic of China

    Z. O. Wang

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  1. L. J. Zhang
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  3. Y. F. Zhang
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Correspondence to Y. Z. Li.

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Zhang, L.J., Wang, Z.O., Zhang, Y.F. et al. A Precise Implementation of Random Access Time Measurement for Embedded SRAM. J. Inst. Eng. India Ser. B 100, 525–528 (2019). https://doi.org/10.1007/s40031-019-00400-4

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  • DOI: https://doi.org/10.1007/s40031-019-00400-4

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