Advertisement

Design of energy-aware interconnects for next generation micro systems

  • Rohit SharmaEmail author
  • Somesh Kumar
S.I. : Visvesvaraya
  • 27 Downloads

Abstract

This paper presents an overview of the problem of surface roughness in ultra-scaled Copper (Cu) interconnects. It is seen that surface roughness can severely degrade the electrical and thermal performance of Cu interconnects. This penalty has largely been ignored that has resulted in fairly optimistic models and estimates. It is in this context that this paper and our ongoing work gains significance. The authors make an attempt to present the big picture with reference to interconnect surface roughness and its implications on various design metrics.

Keywords

High-speed interconnects Surface roughness 3D ICs Electrical performance 

Notes

Acknowledgements

The authors gratefully acknowledge the help and support received from the Visvesvaraya PhD Scheme, Ministry of Electronics and IT and members of the Nanoelectronics Research Lab, IIT Ropar.

References

  1. 1.
    Moore GE (1998) Cramming more components onto integrated circuits. Proc IEEE 86:82–85CrossRefGoogle Scholar
  2. 2.
    Moore GE (2006) Cramming more components onto integrated circuits, reprinted from electronics, volume 38, number 8, April 19, 1965. IEEE Solid State Circuits Soc Newsl 11:33–35CrossRefGoogle Scholar
  3. 3.
    Faggin F (2009) The making of the first microprocessor. IEEE Solid State Circuits Mag 1:8–21CrossRefGoogle Scholar
  4. 4.
    Schaller RR (1997) Moore’s law: past, present and future. IEEE Spectr 34:52–59CrossRefGoogle Scholar
  5. 5.
    Dennard RH, Gaensslen FH, Rideovt VL, Bassous E, Leblanc AR (2007) Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE Solid State Circuits Soc Newsl 12:38–50CrossRefGoogle Scholar
  6. 6.
    Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (1974) Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J Solid State Circuits 9:256–268CrossRefGoogle Scholar
  7. 7.
    Ho R, Mai KW, Horowitz MA (2001) The future of wires. Proc IEEE 89:490–504CrossRefGoogle Scholar
  8. 8.
    Havemann RH, Hutchby JA (2001) High-performance interconnects: an integration overview. Proc IEEE 89:586–601CrossRefGoogle Scholar
  9. 9.
    Saraswat KC, Mohammadi F (1982) Effect of scaling of interconnections on the time delay of VLSI circuits. IEEE J Solid State Circuits 17:275–280CrossRefGoogle Scholar
  10. 10.
    Meindl JD, Chen Q, Davis JA (2001) Limits on silicon nanoelectronics for terascale integration. Science 293:2044–2049CrossRefGoogle Scholar
  11. 11.
    International Technology Working Groups (2013) International technology roadmap for semiconductorsGoogle Scholar
  12. 12.
    Andricacos PC, Uzoh C, Dukovic JO, Horkans J, Deligianni H (1998) Damascene copper electroplating for chip interconnections. IBM J Res Dev 42:567–574CrossRefGoogle Scholar
  13. 13.
    Bowman KA, Alameldeen AR, Srinivasan ST, Wilkerson CB (2009) Impact of die-to-die and within-die parameter variations on the clock frequency and throughput of multi-core processors. IEEE Trans Very Large Scale Integr (VLSI) Syst 17:1679–1690CrossRefGoogle Scholar
  14. 14.
    Kumar S, Kaur S, Bakshi M, Bansal M, Choudhary M, Sharma R (2014) Design space exploration of through silicon vias for high-speed, low loss vertical links. In: 2014 IEEE electrical design of advanced packaging and systems symposium (EDAPS), pp 9–12Google Scholar
  15. 15.
    Alizadeh A, Sarvari R (2015) On temperature dependency of delay for local, intermediate, and repeater inserted global copper interconnects. IEEE Trans Very Large Scale Integr (VLSI) Syst 23:3143–3147CrossRefGoogle Scholar
  16. 16.
    Banerjee K, Mehrotra A (2002) A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans Electron Devices 49:2001–2007CrossRefGoogle Scholar
  17. 17.
    Kumar S, Sharma R (2015) Design space exploration of nanoscale interconnects with rough surfaces, In: 2015 IEEE electrical design of advanced packaging and systems symposium (EDAPS), pp 125–128Google Scholar
  18. 18.
    Cho H, Kapur P, Saraswat KC (2004) Power comparison between high-speed electrical and optical interconnects for interchip communication. J Lightwave Technol 22:2021–2033CrossRefGoogle Scholar
  19. 19.
    Kumar V, Sharma R, Uzunlar E, Zheng L, Bashirullah R, Kohl P et al (2014) Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications. IEEE Trans Compon Packag Manuf Technol 4:1335–1346CrossRefGoogle Scholar
  20. 20.
    Spencer TJ, Saha R, Chen J, Bashirullah R, Kohl PA (2012) Air cavity transmission lines for off-chip interconnects characterized to 40 GHz. IEEE Trans Compon Packag Manuf Technol 2:367–374CrossRefGoogle Scholar
  21. 21.
    Park S (2008) Materials, processes, and characterization of extended air-gaps for the intra-level interconnection of integrated circuits. Ph.D. Dissertation, School of Chemical and Biomolecular Engineering Georgia Institute of Technology, USAGoogle Scholar
  22. 22.
    Triverio P, Grivet-Talocia S, Nakhla MS, Canavero FG, Achar R (2007) Stability, causality, and passivity in electrical interconnect models. IEEE Trans Adv Packag 30:795–808CrossRefGoogle Scholar
  23. 23.
    Chen X (2007) EM modeling of microstrip conductor losses including surface roughness effect. IEEE Microw Wirel Compon Lett 17:94–96CrossRefGoogle Scholar
  24. 24.
    Patrikar RM (2004) Modeling and simulation of surface roughness. Appl Surf Sci 228:213–220CrossRefGoogle Scholar
  25. 25.
    Patrikar RM, Dong CY, Zhuang W (2002) Modelling interconnects with surface roughness. Microelectron J 33:929–934CrossRefGoogle Scholar
  26. 26.
    Leung T, Xiaoxiong G, Braunisch H (2006) Effects of random rough surface on absorption by conductors at microwave frequencies. IEEE Microw Wirel Compon Lett 16:221–223CrossRefGoogle Scholar
  27. 27.
    Gu X, Tsang L, Braunisch H (2007) Modeling effects of random rough interface on power absorption between dielectric and conductive medium in 3-D problem. IEEE Trans Microw Theory Tech 55:511–517CrossRefGoogle Scholar
  28. 28.
    Sain A, Melde KL (2013) Broadband characterization of coplanar waveguide interconnects with rough conductor surfaces. IEEE Trans Compon Packag Manuf Technol 3:1038–1046CrossRefGoogle Scholar
  29. 29.
    Lopez G, Davis J, Meindl J (2009) A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER). In: 2009 IEEE international interconnect technology conference, pp 231–234Google Scholar
  30. 30.
    Morgan SP Jr (1949) Effect of surface roughness on eddy current losses at microwave frequencies. J Appl Phys 20:352–362CrossRefzbMATHGoogle Scholar
  31. 31.
    Tsang L, Braunisch H, Ding R, Gu X (2010) Random rough surface effects on wave propagation in interconnects. IEEE Trans Adv Packag 33:839–856CrossRefGoogle Scholar
  32. 32.
    Yang BB, Kirley M, Booske JH (2011) Study of the effect of nanofabricated surface roughness on conductivity in the terahertz regime with a high-Q resonator. In: 2011 international conference on infrared, millimeter, and Terahertz waves, p 1Google Scholar
  33. 33.
    Chawla JS, Gall D (2009) Specular electron scattering at single-crystal Cu(001) surfaces. Appl Phys Lett 94:252101–252103CrossRefGoogle Scholar
  34. 34.
    Kumar S, Sharma R (2016) Analytical model for resistivity and mean free path in on-chip interconnects with rough surfaces. IEEE Trans Emerg Top Comput 6:233–243CrossRefGoogle Scholar
  35. 35.
    Sondheimer EH (2001) The mean free path of electrons in metals. Adv Phys 50:499–537CrossRefGoogle Scholar
  36. 36.
    Fuchs K (1938) The conductivity of thin metallic films according to the electron theory of metals. Math Proc Camb Philos Soc 34:100–108CrossRefGoogle Scholar
  37. 37.
    Kumar S, Sharma R (2018) Analytical modeling and performance benchmarking of on-chip interconnects with rough surfaces. IEEE Trans Multi Scale Comput Syst 4(3):272–284CrossRefGoogle Scholar
  38. 38.
    Leunissen LHA, Zhang W, Wu W, Brongersma SH (2006) Impact of line edge roughness on copper interconnects. J Vac Sci Technol B Microelectron Nanometer Struct Process Meas Phenom 24:1859–1862CrossRefGoogle Scholar
  39. 39.
    García-Valenzuela A, Bruce NC, Kouznetsov D (1998) An investigation into the applicability of perturbation techniques to solve the boundary integral equations for a parallel-plate capacitor with a rough electrode. J Phys D Appl Phys 31:240–251CrossRefGoogle Scholar
  40. 40.
    Hinaga MKS, Anmula P, Drewniak J (2009) Effect of conductor surface roughness upon measured loss and extracted values of PCB laminate material dissipation factor. In: IPC APEX EXPO technical conference, USAGoogle Scholar
  41. 41.
    Guo X, Jackson DR, Koledintseva MY, Hinaga S, Drewniak JL, Chen J (2014) An analysis of conductor surface roughness effects on signal propagation for stripline interconnects. IEEE Trans Electromagn Compat 56:707–714CrossRefGoogle Scholar
  42. 42.
    Zhu Z, White J (2005) FastSies: a fast stochastic integral equation solver for modeling the rough surface effect. In: Presented at the proceedings of the 2005 IEEE/ACM international conference on computer-aided design, San Jose, CAGoogle Scholar
  43. 43.
    Zhang H, Krooswyk S, Ou J (2015) High speed digital design: design of high speed interconnects and signaling. Morgan Kaufmann Publishers Inc., BurlingtonGoogle Scholar
  44. 44.
    Stucchi M, Bamal M, Maex K (2007) Impact of line-edge roughness on resistance and capacitance of scaled interconnects. Microelectron Eng 84:2733–2737CrossRefGoogle Scholar
  45. 45.
    Yamaguchi A, Steffen R, Kawada H, Iizumi T, Sugimoto A (2007) A discussion on how to define the tolerance for line-edge or linewidth roughness and its measurement methodology. IEEE Trans Semicond Manuf 20:549–555CrossRefGoogle Scholar
  46. 46.
    Bruce NC, García-Valenzuela A, Kouznetsov D (1999) Rough-surface capacitor: approximations of the capacitance with elementary functions. J Phys D Appl Phys 32:2692–2702CrossRefGoogle Scholar
  47. 47.
    Bruce NC, García-Valenzuela A (2007) Capacitance of a plate capacitor with one band-limited fractal rough surface. Rev Mex Física 53:296–302Google Scholar
  48. 48.
    Bruce NC, García-Valenzuela A, Kouznetsov D (2000) The lateral resolution limit for imaging periodic conducting surfaces in capacitive microscopy. J Phys D Appl Phys 33:2890–2898CrossRefGoogle Scholar
  49. 49.
    Kumar S, Sharma R (2016) Performance modeling and broadband characterization of chip-to-chip interconnects with rough surfaces. In: 2016 IEEE 18th electronics packaging technology conference (EPTC), pp 629–632Google Scholar
  50. 50.
    Seiler P, Klein B, Plettemeier D (2016) Internal inductance correction for permittivity measurements of planar transmission lines. In: 2016 international symposium on antennas and propagation (ISAP), pp 732–733Google Scholar
  51. 51.
    Rautio JC, Rautio BJ, Arvas S, Horn AF, Reynolds JW (2010) The effect of dielectric anisotropy and metal surface roughness. In: 2010 Asia-Pacific microwave conference, pp 1777–1780Google Scholar
  52. 52.
    Volos S (2015) Memory systems and interconnects for scale-out servers.Ph.D. Dissertation, EPFLGoogle Scholar
  53. 53.
    Venkatesan R, Davis JA, Meindl JD (2003) Compact distributed RLC interconnect models—part IV: unified models for time delay, crosstalk, and repeater insertion. IEEE Trans Electron Devices 50:1094–1102CrossRefGoogle Scholar
  54. 54.
    Hall SH, Heck HL (2009) Advanced signal integrity for high-speed digital designs. Wiley-IEEE Press, New YorkCrossRefGoogle Scholar
  55. 55.
    Wong SC, Lee GY, Ma DJ (2000) Modeling of interconnect capacitance, delay, and crosstalk in VLSI. IEEE Trans Semicond Manuf 13:108–111CrossRefGoogle Scholar
  56. 56.
    Stellari F, Lacaita AL (2000) New formulas of interconnect capacitances based on results of conformal mapping method. IEEE Trans Electron Devices 47:222–231CrossRefGoogle Scholar
  57. 57.
  58. 58.
  59. 59.
    Yuan CQ, Li J, Yan XP, Peng Z (2003) The use of the fractal description to characterize engineering surfaces and wear particles. Wear 255:315–326CrossRefGoogle Scholar
  60. 60.
    Kumar V, Sharma R, Chen J, Kapoor A, Bashirullah R, Kohl P et al (2012) Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities. In: 2012 IEEE international interconnect technology conference, pp 1–3Google Scholar
  61. 61.
    Ismail YI, Friedman EG, Neves JL (2000) Equivalent Elmore delay for RLC trees. IEEE Trans Comput Aided Des Integr Circuits Syst 19:83–97CrossRefGoogle Scholar
  62. 62.
    Lü X (2009) Thermal conductivity modeling of copper and tungsten damascene structures. J Appl Phys 105:094301–094312CrossRefGoogle Scholar
  63. 63.
    Liu HD, Zhao YP, Ramanath G, Murarka SP, Wang GC (2001) Thickness dependent electrical resistivity of ultrathin (< 40 nm) Cu films. Thin Solid Films 384:151–156CrossRefGoogle Scholar
  64. 64.
    Timoshevskii V, Ke Y, Guo H, Gall D (2008) The influence of surface roughness on electrical conductance of thin Cu films: an ab initio study. J Appl Phys 103:113705-4CrossRefGoogle Scholar
  65. 65.
    Stucchi M, Roussel PJ, Tokei Z, Demuynck S, Groeseneken G (2011) A comprehensive LER-aware TDDB lifetime model for advanced Cu interconnects. IEEE Trans Device Mater Reliab 11:278–289CrossRefGoogle Scholar
  66. 66.
    Kapur P, McVittie JP, Saraswat KC (2002) Technology and reliability constrained future copper interconnects. I. Resistance modeling. IEEE Trans Electron Devices 49:590–597CrossRefGoogle Scholar
  67. 67.
    Kapur P, Chandra G, McVittie JP, Saraswat KC (2002) Technology and reliability constrained future copper interconnects. II. Performance implications. IEEE Trans Electron Devices 49:598–604CrossRefGoogle Scholar
  68. 68.
    Curran B, Ndip I, Guttowski S, Reichl H (2010) A methodology for combined modeling of skin, proximity, edge, and surface roughness effects. IEEE Trans Microw Theory Tech 58:2448–2455CrossRefGoogle Scholar
  69. 69.
    Horn AF, Reynolds JW, Rautio JC (2010) Conductor profile effects on the propagation constant of microstrip transmission lines. In: 2010 IEEE MTT-S international microwave symposium, pp 868–871Google Scholar
  70. 70.
    Chen Q, Choi HW, Wong N (2009) Robust simulation methodology for surface-roughness loss in interconnect and package modelings. IEEE Trans Comput Aided Des Integr Circuits Syst 28:1654–1665CrossRefGoogle Scholar
  71. 71.
    Namba Y (1968) Electrical conduction of thin metallic films with rough surface. J Appl Phys 39:6117–6118CrossRefGoogle Scholar
  72. 72.
    Pande RS, Jalgaonkar A, Patrikar RM (2007) A 3-D FEM based extractor for MEMS inductor with Monte-Carlo sampling. In: 2007 international workshop on physics of semiconductor devices, pp 710–713Google Scholar
  73. 73.
    Joshi AJ, Lopez GG, Davis JA (2007) Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing. IEEE Trans Very Large Scale Integr (VLSI) Syst 15:990–1002CrossRefGoogle Scholar
  74. 74.
    Pasricha S, Kurdahi FJ, Dutt N (2010) Evaluating carbon nanotube global interconnects for chip multiprocessor applications. IEEE Trans Very Large Scale Integr (VLSI) Syst 18:1376–1380CrossRefGoogle Scholar

Copyright information

© CSI Publications 2019

Authors and Affiliations

  1. 1.Department of Electrical EngineeringIndian Institute of Technology RoparRupnagarIndia
  2. 2.ABV - Indian Institute of Information Technology and Management GwaliorGwaliorIndia

Personalised recommendations