LORAx: A High-speed Energy-efficient Lower-Order Rounding-based Approximate Multiplier


Applications such as image, audio, and video processing are tolerant to certain amounts of error. This tolerance/resiliency can be exploited to construct approximate circuits with improved design parameters such as area, power, and delay. This paper presents a high-speed yet energy-efficient approximate multiplier for low-power applications. In the proposed scheme, the operands are divided into accurate (significant) and rounded (insignificant) sections at half of the operand bit-length. Further, simplified multiplication operations are performed between these sections to obtain the final product. The proposed multiplier architecture involves an accurate small width multiplier as well as shifter blocks, which leads to delay- and energy-efficient architecture. The performance of proposed multiplier over the existing is evaluated by coding the designs in Verilog implementing on Artix7 family XC7A100TCSG324 FPGA device using Xilinx ISE tool chain. The simulation results show 23–31% and up to 26% in delay and energy savings, respectively, over the existing approximate architectures.

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Correspondence to Bharat Garg.

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Satti, P., Agrawal, P. & Garg, B. LORAx: A High-speed Energy-efficient Lower-Order Rounding-based Approximate Multiplier. Natl. Acad. Sci. Lett. (2021). https://doi.org/10.1007/s40009-020-01036-5

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  • Arithmetic design
  • Approximate architecture
  • High-speed
  • Energy-efficient design
  • Multipliers
  • Image processing