Abstract
This work exhibits an area-efficient negative charge pump (NCP) solution for an on-chip localized body bias generator (BBG) which has almost zero settling time for use in critical path replicas clearance. Also, the proposed circuit incorporates process and voltage compensation and dynamic energy optimization. Its temperature variation trend is regular and justified. The negative charge pump is implemented using Cadence Virtuoso for design and Eldo for simulation with 28-nm ultra thin body and box—fully depleted silicon on insulator (UTBB-FDSOI) for 0.85–1.3 V inputs. The implemented design is single-stage design, so it is area efficient. Its area occupancy is 2.94 µm2 and power occupancy is 34 µW. Negative charge pump-based body bias generator can be sprinkled with standard cells to enhance performance and robustness of the design.
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Acknowledgements
The authors would like to thank STMicroelectronics, India for CAD tools and access to technology.
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Jain, A., Khare, K. & Tripathi, A.K. FDSOI-Based Area and Power-Efficient Robust Negative Charge Pump for Localized Body Bias Generator. Natl. Acad. Sci. Lett. 42, 345–349 (2019). https://doi.org/10.1007/s40009-018-0752-9
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DOI: https://doi.org/10.1007/s40009-018-0752-9