Abstract
Most of the authentication protocols have modular multi-exponentiation (MME) as their core operation in the verification step. Triple modular-multi exponentiation playing a vital role in Batch verification schemes. This work proposes energy-efficient modular-multi exponential techniques that compute triple modular exponentiation. Two unique techniques are designed to calculate the MME with integrated confusion mechanisms in an efficient manner. The confusion factor has been introduced at two levels for improving security. Currently, the most common side-channel attacks (SCAs) are only hardware-secured. This article has also presents an algorithmic way of counteracting the SCAs. The results indicate that the throughput has increased by an order of 3.3% by reducing the power by 3.35% and saving the energy by an order of 3.35%. The proposed techniques are 72% more efficient(efficiency \(\eta =1.72\)) than the state-of-the-art. One of the significant contributions of the presented MME techniques is that they are hardware compatible. We have implemented the proposed techniques on FPGA using Vivado 22.2 on VC707 evaluation boards.
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We would like to thank the Department of Science and Technology, India for funding this research under ICPS Grant with Grant id: DST/ICPS/CPS-Individual/2018/895.
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Vollala, S. Energy efficient triple-modular exponential techniques for batch verification schemes. J Cryptogr Eng (2024). https://doi.org/10.1007/s13389-024-00348-2
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DOI: https://doi.org/10.1007/s13389-024-00348-2