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A Novel Active Inductor Based Low Noise Amplifier for Analog Front End of Bio-medical Applications

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This work contributes an area-effective low-noise amplifier design with a vast voltage gain range for a wide frequency range. The novel low-noise amplifier has an input stage, a common-gate stage, and another stage of the common-source technique. It is designed using the current mirror, the current bleeding network, and a new active inductor circuit. The noise-canceling network leads to a reduction of noise and power. The current-bleeding network improves the trans-conductance and provides a reduction in overall noise. Active inductors are crucial for achieving maximal gain, extensive bandwidth values, and low power consumption. Body-biasing technique has improved overall performance of the design. The novel low-noise amplifier is simulated and designed at a 0.5 V input voltage cadence virtuoso GPDK 90 nm and GPDK 45 nm complementary metal-oxide semiconductors (CMOS). The power dissipation of the novel active inductor (AI) is 416 µW with an optimized gain value, a small area requirement, and inductance values that varies with different W/L ratios of AI transistors. Power consumption of this low-noise amplifier is 4.85 mW, with optimized S-parameters values. Additionally, a small area and an optimized gain value also adds to the immense potential offered by proposed designs compared to the state-of-the-art low-noise amplifiers.

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Low noise amplifiers


Active inductor


Analog front end


Design rule checking


Ratio of width and length




Current mirror


Noise canceling


Layout versus schematic


Passive inductor

FoM1, FoM2 :

Figure of Merits


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The authors are grateful to an Indraprastha Research Fellowship from Guru Gobind Singh Indraprastha University.

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Nomenclature for different parameters across analysis sections.


Assumptions across Eqs. (15)–(30) and small signal equivalent circuit Fig. 3 for simplification of calculation

Assumed variables are C11, C12, C21, C22, C31, C32, C1–C5, ga–gd, a–g, m, v


Nomenclature of proposed designs


Naming for transistors in Fig. 2a of LNA

R1–R4 or g1–g4

Resistance or conductance used in Eqs. (15)–(17), (21), (23), (26)–(31) and Figs. 2a, 3b of LNA

N1–N7, P1–P2

NMOS and PMOS transistors across Fig. 2b of proposed AI

gdsx or r0x

Conductance or resistance between drain and source terminal of transistor in the

Equations (2)–(7), (13)–(15), (17), (23), (29)–(31) and Fig. 3a, b


Trans–conductance of transistor across Eqs. (2)–(3), (5)–(6), (13)–(15), (17)– (20), (22)–(28), (31) and Fig. 3a, b


Trans-conductance across the substrate terminal of the transistor in Eqs. (15) , (17)–(19) and Fig. 3b


Capacitance between gate and source terminal of transistor in Eqs. (1),(3), (5)–(8), (13), (15), (20),(29), (30) and Fig. 3a, b


Capacitance between the gate and drain terminal of transistor across Eqs. (15), (20), (22), (24)–(30) and Fig. 3a, b


Capacitance between drain and substrate terminal of transistor in Fig. 3

Where x is stand for referring to transistors. The x can be N1–N7, P1–P2 for AI transistors and 1–10 numbering for M1–M10 transistors of LNA

R, L and C

Equivalent Resistance, inductance, and capacitance used in Sect. 2.2 across a circuit

YIN (Yai), Yai1and Yai2

Admittance for proposed AI design, AI1 and AI2 across LNA utilized in the Eqs. (10), (11) and Fig. 3a–c

ZAI, Zai1 and Zai2

Impedance for proposed AI design, AI1 and AI2 across LNA in the Fig. 3

Gai, gai1 and gai2

Conductance across proposed AI circuit; AI1 and AI2 across LNA in Eqs. (9)–(12), (15)–(16), (26)–(27), (31) and Fig. 3

Cai, Cp

Total Capacitance for proposed AI design and equivalent RLC circuit of AI across Eqs. (9)–(12) and Fig. 3

Lai, Lp

Total Inductance for proposed AI design and equivalent RLC circuit of AI in the Eqs. (9)–(12) and Fig. 3

Bai1, Bai2

Susceptance in Eq. (15) and Fig. 3 across proposed AI1 and AI2 of LNA


Frequency in Eqs. (9)–(11), (13), (29) – (30) and Fig. 3 across the proposed design


Noise figure in Eqs. (14), (31)–(33) across proposed designs


Quality factor in the Eq. (13) across Proposed AI


Quality factor calculated using total capacitor and inductor across Eqs. (29)–(30) of proposed designs


Stability factor in Eq. (28) across proposed designs

S11, S12, S21, S22

S-parameters in Eqs. (24)–(27) of novel LNA design


Output third order-intercept point in the Sect. 4


Voltage and current parameters


Input voltage used across Eqs. (16), (21), (23) and Fig. 2, 3(b) of LNA


Output voltage in Eqs. (22)–(23) and Fig. 3(b) of LNA


DC voltage in Fig. 13, 5 and Sects. 24


Bias Voltage in Fig. 2a and Sect.  3 and 4


Voltage across Impedance ZAI or admittance Yin (Yai) in Eq. (8) and Fig. 3 of AI


Voltage at different nodes of AI utilized across the Eqs. (1)–(8) and Fig. 3a

Va, Vbb, Vc–Ve

Voltage at different nodes of LNA design in Eqs. (16)–(22) and Fig. 3b


Input current in Eq. (21) and Fig. 3 of proposed LNA


Output current in Eq. (22) and Fig. 3b of proposed LNA


Current across Impedance ZAI or admittance Yin (Yai) in Eq. (8) and Fig. 3a of AI

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Pritty, Jhamb, M. A Novel Active Inductor Based Low Noise Amplifier for Analog Front End of Bio-medical Applications. Arab J Sci Eng (2024).

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