Effect of High dV/dt on Voltage Stress Across Inductor Turns and Utilization of Additive Manufacturing for Mitigation

Abstract

Higher switching frequencies and faster switching speeds in power electronics were realized as a result of using wide bandgap (SiC, GaN) devices. Although having higher dV/dt can be beneficial in power electronics application, insulation reliability of inductors can be affected due to the inductor’s parasitic capacitances’ influence. Parasitic capacitances can change the inductor’s impedance drastically at high switching frequencies. Higher dV/dt across an inductor can cause higher voltage stress and less uniform voltage distribution across its turns. Thus, inductor winding insulation can be at risk in medium or high voltage applications under high dV/dt. A convenient solution is to add filters in the circuit to slow down the switching (reduce the dV/dt) which means some advantages of using wide bandgap devices will be lost. Hence, the approach of utilizing additive manufacturing to fabricate the inductor winding and optimize the parasitics is introduced instead of slowing down the switching. In this approach, the voltage stress is distributed more evenly across the inductor’s winding which reduces the maximum voltage stress across some turns. A 20 kV inductor is developed to showcase the proposed approach. Experimental results show that the peak voltage stress between inductor turns has reduced by over 10$\%$. Furthermore, the maximum voltage stress difference between inductor turns has reduced 67$\%$.