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A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier

  • Research Article-Electrical Engineering
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Abstract

This paper presents a new compact design for low-voltage low-power four-quadrant current mode analog multiplier based on floating-gate transistors. The proposed multiplier exploits multi-input and square-law characteristics of floating-gate transistor operating in saturation mode to generate addition and squaring operation of input currents. The extra current square terms and offset current component are eliminated with the help of three n-channel metal–oxide–semiconductor transistors operating in saturation region. Further, to increase the operating range of the proposed multiplier, two of the metal–oxide–semiconductor transistors are replaced by floating-gate transistors. These transistors provide low power operation along with threshold voltage controllability while offering the advantage of simple circuitry. To evaluate the circuit operation, simulations are done in Ltspice with the help of 180 nm technology file. The proposed circuit operates at 1 V (± 0.5 V) and consumes total power and static power of 24.56 µW and 3.93 µW, respectively. The circuit operates with a maximum linearity error of 0.88%, a total harmonic distortion of 0.39% at 1 MHz and offers a bandwidth of 919.22 MHz. In order to obtain a fair comparison, various state-of-the-art multipliers reported in the literature have been simulated using similar platform as used by the authors for their proposed work. These simulation results confirm that the proposed multiplier operates at the lowest supply voltage while consuming least quiescent power. Further, it has also been observed that the proposed circuit requires current mirrors and biasing voltage sources only, as compared to complex current addition and subtraction circuits along with biasing current sources required in existing multiplier circuits.

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Abbreviations

% Error|λ :

% Error in output current due to channel length modulation effect

% Error|∆ R :

% Error in output current due to mismatch in resistances

% Error|∆ µ :

% Error in output current due to mobility degradation

% Error|∆ K :

% Error in output current due to transconductance mismatch

V E :

An intermediate voltage term, used for simplicity of equations and is equal to VB/3–Vtn–Vss

V B :

Biasing voltage

λ :

Channel length modulation parameter

V G :

Gate voltage

I x, I y :

Input currents

R L :

Load resistor

µ n :

Mobility of electron

V ss :

Negative supply voltage

I out :

Output current

I out ′|λ :

Output current with channel length modulation effect

I out ′|∆ µ :

Output current with mobility degradation effect

I out ′|∆ R :

Output current with variations in resistances

I out ′|∆ K :

Output current with variations in transconductance parameter

V dd :

Positive supply voltage

R a, R b, R c and R d :

Resistors connected at secondary input gate terminals of FGMOS

I DS n sat. :

Saturation drain current of nth transistor

V tn :

Threshold voltage of n-channel transistor

V tp :

Threshold voltage of p-channel transistor

θ :

Technological parameter that is inversely proportional to the oxide thickness

K n :

Transconductance parameter of n-channel transistor

K n|∆ µ :

Transconductance parameter of n-channel transistor with mobility degradation

V DS :

Voltage difference between drain and source terminals of a transistor

V GS :

Voltage difference between gate and source terminals of a transistor

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Acknowledgements

Authors would like to acknowledge Prof. Raj Senani for his valuable guidance and continuous support during the work.

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Authors and Affiliations

  1. Netaji Subhas University of Technology, Delhi, 110078, India

    Bhawna Aggarwal & Ranveer Dhawan

  2. IIT Delhi, Hauz Khas, Delhi, 110016, India

    Niharika Narang

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  1. Bhawna Aggarwal
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  2. Ranveer Dhawan
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  3. Niharika Narang
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Correspondence to Bhawna Aggarwal.

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Aggarwal, B., Dhawan, R. & Narang, N. A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier. Arab J Sci Eng 47, 14455–14470 (2022). https://doi.org/10.1007/s13369-022-06742-4

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