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A New pW CMOS Sub-Hertz Timer

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A low-voltage and ultra-low power sub-Hertz timer using transistor operating in sub-threshold region is proposed. The sub-Hertz operation is achieved by controlling the amount of currents charging and discharging the timer’s capacitor instead of using large passive components. Pulse width modulation is accomplished by sizing the transistors in charging and discharging control blocks. The timer is working from a single supply voltage of as low as 0.4 V. The circuit is designed in a standard CMOS 150 nm and simulated using Cadence. Simulation results show an oscillation frequency of as low as 0.0217 Hz (a period of 46 s) while using integrable capacitor (100 pF). Its average power consumption for one period is 13.91 pW.

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The authors would like to thank the support of KAUST-KFUPM Initiative (KKI) program project #1.

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Correspondence to Hussain Alzaher.

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Shahid, H., Alzaher, H. A New pW CMOS Sub-Hertz Timer. Arab J Sci Eng 45, 1379–1384 (2020).

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