AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

  • Baby Chellam Manjith 
  • Natarajan Ramasubramanian 
Research Article - Computer Engineering and Computer Science
  • 61 Downloads

Abstract

With the increase in computation and data storage in cloud servers, the need for a dedicated hardware accelerator for encryption is arising in order to reduce the processor job. High-throughput and resource-optimized implementation of 128-bit Advanced Encryption Standard (AES 128-bit), which can be used as an accelerator, is presented in this article. Memory partitioning is done in order to assign multiple ports for parallel data access. After the algorithm is pipelined and unrolled at each operation on the basis of the analyzed latency and initiation interval of different operations, for each critical path delays, a new multistage single initiation interval sub-pipelined architecture is proposed to make the initiation interval to one for lowest path delay. As a result, all operations in AES can be initiated within one clock cycle and can accept input in every clock cycle. The proposed method when simulated, synthesized, and implemented on the latest XC7VX690T device gives a throughput of 104.06 Gbps at a maximum frequency of 813 MHz and 1.23-ns path delay. The resource utilization is lower when compared with other counterparts. The proposed system gives 30.74 Mbps efficiency on XC5VLX85 device, which is 27.13% more than the best efficiency reported in a previous work.

Keywords

AES FPGA Pipelining Memory partitioning Latency Initiation interval Path delay 

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Copyright information

© King Fahd University of Petroleum & Minerals 2017
corrected publication March 2018

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringNational Institute of TechnologyTiruchirappalliIndia

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