Abstract
Today most of the systems run general purpose applications which have non-uniform memory accesses. This work proposes a new technique for last level cache (LLC) organization, named as hashed cache using overuse distance for ways sharing (HCOWS), to reorganize the cache memory of a system to contribute better performance in multicore systems. The proposed HCOWS technique can be applied on multicore platforms, to improve performance of cache memory and hence of a system for myriad of general purpose applications. A new mapping technique is employed using universal hashing which is highly random. This scheme employs sharing of ways instead of set sharing. This work evaluates the performance of cache hierarchy using average memory access time. HCOWS scheme-based system has given better miss rate reduction when compared with the simple baseline system by 33 % in dual core, 37 % in quad core and 41 % in octa core, which substantiates the fact that increased number of cores dispenses better performance. The proposed scheme has high impact on miss rate reduction with the increase in size of LLC rather than the associativity of LLC.
Article PDF
We’re sorry, something doesn't seem to be working properly.
Please try refreshing the page. If that doesn't work, please contact support so we can address the problem.
References
Geer D.: Chip makers turn to multicore processors. Computer 38(5), 11–13 (2005)
Gorder P.F.: Multicore processors for science and engineering. Comput. Sci. Eng. 9(2), 3–7 (2007)
Hennessy J.L., Patterson D.A.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann, Burlington (2011)
Golander A., Levison N., Heymann O., Briskman A., Wolski M.J., Robinson E.F.: A cost-efficient l1–l2 multicore interconnect: performance, power, and area considerations. IEEE Trans. Circuits Syst. I Regul. Pap. 58(3), 529–538 (2011)
Geer D.: Chip makers turn to multicore processors. Computer 38(5), 11–13 (2005)
Balasubramonian R., Jouppi N.P., Muralimanohar N.: Multi-core cache hierarchies. Synth. Lect. Comput. Archit. 6(3), 1–153 (2011)
Deepika, B.L.; Lee, B.K.: Hybrid-way cache for mobile processors. In: 2011 Eighth International Conference on Information Technology: New Generations (ITNG), pp. 707–712. IEEE (2011)
Davanam, N.; Lee, B.K.: Towards smaller-sized cache for mobile processors using shared set-associativity. In: 2010 Seventh International Conference on Information Technology: New Generations (ITNG), pp. 1–6. IEEE (2010)
Tao, J.; Kunze, M.; Karl, W.: Evaluating the cache architecture of multicore processors. In: 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2008. PDP, pp 12–19. IEEE (2008)
Guibas L.J., Szemeredi E.: The analysis of double hashing. J. Comput. Syst. Sci. 16(2), 226–274 (1978)
Qureshi, M.K.; Thompson, D.; Patt, Y.N.: The v-way cache: demand-based associativity via global replacement. In: 32nd International Symposium on Computer Architecture, 2005. ISCA’05. Proceedings, pp. 544–555. IEEE (2005)
Manikantan, R.; Rajan, K.; Govindarajan, R.: Nucache: an efficient multicore cache organization based on next-use distance. In: 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), pp. 243–253. IEEE (2011)
Ramakrishna M.V., Fu E., Bahcekapili E.: Efficient hardware hashing functions for high performance computers. IEEE Trans. Comput. 46(12), 1378–1381 (1997)
Panneton F., L’ecuyer P., Matsumoto M.: Improved long-period generators based on linear recurrences modulo 2. ACM Trans. Math. Softw. (TOMS) 32(1), 1–16 (2006)
Hill M.D., Marty M.R.: Amdahl’s law in the multicore era. Computer 41(7), 33–38 (2008)
Zhan, D.; Jiang, H.; Seth, S.C.: Stem: Spatiotemporal management of capacity for intra-core last level caches. In: 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 163–174. IEEE (2010)
Zhang L., Parker M., Carter J.: Efficient address remapping in distributed shared-memory systems. ACM Trans. Archit. Code Optim. (TACO) 3(2), 209–229 (2006)
Sanchez, D.; Kozyrakis, C.: The zcache: decoupling ways and associativity. In: 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 187–198. IEEE (2010)
Seznec, A.: A case for two-way skewed-associative caches. In: ACM SIGARCH Computer Architecture News, vol. 21, pp. 169–178. ACM (1993)
Hallnor, E.G.; Reinhardt, S.K.: A fully associative software-managed cache design. In: ACM SIGARCH Computer Architecture News, vol. 28, pp. 107–116. ACM (2000)
Bobbala, L.D.; Debnath, M.; Lee, B.K.: Composite pseudo associative cache with victim cache for mobile processors. PhD thesis, University of Texas at San Antonio (2010)
Wu X., Li J., Zhang L., Speight E., Rajamony R., Xie Y.: Design exploration of hybrid caches with disparate memory technologies. ACM Trans. Archit. Code Optim. (TACO) 7(3), 15 (2010)
Binkert N., Beckmann B., Black G., Reinhardt S.K., Saidi A., Basu A., Hestness J., Hower D.R., Krishna T., Sardashti S. et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)
Bienia, C.; Kumar, S.; Singh, J.P.; Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72–81. ACM (2008)
Woo, S.C.; Ohara, M.; Torrie, E.; Singh, J.P.; Gupta, A.: The splash-2 programs: characterization and methodological considerations. In: ACM SIGARCH Computer Architecture News, vol. 23, pp. 24–36. ACM (1995)
Author information
Authors and Affiliations
Corresponding author
About this article
Cite this article
Singh, A.K., Geetha, K., Vollala, S. et al. Efficient Utilization of Shared Caches in Multicore Architectures. Arab J Sci Eng 41, 5169–5179 (2016). https://doi.org/10.1007/s13369-016-2197-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s13369-016-2197-0