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Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor-Transistor Hybrid FPGA Architecture

Arabian Journal for Science and Engineering volume 41, pages 3035–3049 (2016)Cite this article

Abstract

Field-programmable gate arrays (FPGAs) have come a long way from being used as glue logic to complete system solution. This is mainly because of their generalized reconfigurable nature, low non-recurring engineering (NRE) cost, and rapid time to market. However, their advantages come at the cost of larger area and higher power consumption eventually making them unsuitable for area and power critical applications. In this work, we propose a novel memristor-transistor hybrid FPGA architecture. Memristor-transistor-based building blocks of FPGA architecture are designed and simulated using HSPICE in this work. Results show that hybrid blocks on average take 30.3 % less area and consume 64.3 % less power compared to transistor-only blocks. Hybrid blocks are combined together to construct logic blocks [i.e., look-up tables (LUTs) and configurable logic blocks] and routing switches of hybrid FPGA architecture. Furthermore, a generalized exploration environment is developed to explore the effect of LUT size on the area and power consumption of memristor-transistor hybrid FPGA architecture. For experimental purpose, sixteen largest MCNC benchmarks are used and LUT size is varied from three to seven. Experimental results show that LUT-4 gives the best area and power results for memristor-transistor hybrid FPGA architecture.

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References

  1. Chua L.: Memristor-the missing circuit element. Circuit Theory IEEE Trans. 18(5), 507–519 (1971)

    Article  Google Scholar 

  2. Williams R.: How we found the missing memristor. Spectrum IEEE 45(12), 28–35 (2008)

    Article  Google Scholar 

  3. Strukov D.B., Snider G.S., Stewart D.R., Williams R.S.: The missing memristor found. Nature 453(7191), 80–83 (2008)

    Article  Google Scholar 

  4. Sarwar S., Saqueb S., Quaiyum F., Rashid A.-U.: Memristor-based nonvolatile random access memory: Hybrid architecture for low power compact memory design. Access IEEE 1, 29–34 (2013)

    Article  Google Scholar 

  5. Vourkas, I.; Sirakoulis, G.C.: Incorporating memristors in currently established logic circuit architectures: design considerations and challenges. In: Workshop on Memristor Technology, Design, Automation And Computing (MemTDAC) Affiliated with the HiPEAC 2014 conference, (Jan 2014)

  6. Kuon I., Tessier R., Rose J.: FPGA architecture: Survey and challenges. Found. Trends Electron. Des. Autom. 2(2), 135–253 (2008)

    Article  Google Scholar 

  7. Yang, S.: Logic synthesis and optimization benchmarks user guide, version 3.0, (1991)

  8. Scaramuzzo, J.: The flash transformed data center. In: Fifth Annual Non-Volatile Memories Workshop, (2014)

  9. Kvatinsky, S.; Friedman, E.; Kolodny, A.; Weiser, U.: TEAM: Threshold adaptive memristor model. In: Circuits and Systems I: Regular Papers, IEEE Transactions, 60(1), 211–221 (2013)

  10. Biolek D., Ventra M.D., Pershin Y.V.: Reliable spice simulations of memristors, memcapacitors and meminductors. Radioengineering 22(4), 945–968 (2013)

    Google Scholar 

  11. Zaplatilek, K.: Memristor modeling in matlab&simulink. In: European Computing Conference, 2010, pp. 62–67.

  12. Pershin Y., Di Ventra M.: Practical approach to programmable analog circuits with memristors. Circuits Syst. I Regul. Papers IEEE Trans. 57(8), 1857–1864 (2010)

    Article  MathSciNet  Google Scholar 

  13. Ioannis Vourkas G.C.S.: Memristor-based combinational circuits: a design methodology for encoders/decoders. Microelectron. J. 45, 59–70 (2014)

    Article  Google Scholar 

  14. Kvatinsky, S.; Kolodny, A.; Weiser, U.; Friedman, E.: Memristor-based IMPLY logic design procedure. In: Computer Design (ICCD), 2011 IEEE 29th International Conference on, Oct 2011, pp. 142–147.

  15. Kvatinsky, S.; Wald, N.; Satat, G.; Kolodny, A.; Weiser, U.; Friedman, E.: Mrl memristor ratioed logic. In: Cellular Nanoscale Networks and Their Applications (CNNA), 2012 13th International Workshop on. IEEE, Aug 2012, pp. 1–6.

  16. Kvatinsky S., Belousov D., Liman S., Satat G., Wald N., Friedman E., Kolodny A., Weiser U.: Magic memristor aided logic. Circuits Syst. II Express Br. IEEE Trans. 61(11), 895–899 (2014)

    Article  Google Scholar 

  17. Hamdioui, S.; Xie, L.; Nguyen, H.A.D.; Taouil, M.; Bertels, K.; Corporaal, H.; Jiao, H.: Memristor based computation-in-memory architecture for data-intensive applications. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1718–1725 (2015)

  18. Xia, Q.; Robinett, W.; Cumbie, M.W.; Banerjee, N.; Cardinali, T.J.; Yang, J.J.; Wu, W.; Li, X.; Tong, W.M.; Strukov, D.B.; Snider, G.S.; Medeiros-Ribeiro, G.; Williams, R.S.: Memristor CMOS hybrid integrated circuits for reconfigurable logic. Nano Letters, 9(10), 3640–3645, (2009), pMID: 19722537. [Online]. Available:

  19. Cong, J.; Xiao, B.: mrfpga: A novel FPGA architecture with memristor-based reconfiguration. In: Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on, June 2011, pp. 1–8.

  20. Strukov, D.; Mishchenko, A.: Monolithically stackable hybrid FPGA. In: Design Automation and Test in Europe, pp. 661–666 (2010)

  21. Almurib, H.; Kumar, T.; Lombardi, F.: A memristor-based LUT for FPGAs. In: Nano/Micro Engineered and Molecular Systems (NEMS), 2014 9th IEEE International Conference on, April 2014, pp. 448–453.

  22. Hasan, R.; Taha, T.: Memristor crossbar based programmable interconnects. In: VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, July 2014, pp. 94–99.

  23. Wang, W.; Jing, T.; Butcher, B.: FPGA based on integration of memristors and cmos devices. In: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, May 2010, pp. 1963–1966.

  24. Choi K.H., Duraisamy N., Awais M.N., Muhammad N.M., Kim H.-C., Jo J.: Investigation on switching behavior of zro2 thin film for memory device applications. Mater. Sci. Semicond. Proc. 16, 1285–1291 (2013)

    Article  Google Scholar 

  25. Chen, Y.; Zhao, J.; Xie, Y.: 3d-nonfar: Three-dimensional non-volatile FPGA architecture using phase change memory. In: Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on, Aug 2010, pp. 55–60.

  26. Vourkas I., Sirakoulis G.: A novel design and modeling paradigm for memristor-based crossbar circuits. Nanotechnol. IEEE Trans. 11(6), 1151–1159 (2012)

    Article  Google Scholar 

  27. Farooq, U.; Aslam, M.: Design and implementation of basic building blocks of FPGA using memristor-transistor hybrid approach. In: Fifth International Conference on Innovative Computing Technology (INTECH), 2015, May 2015, pp. 142–147.

  28. Kvatinsky, S.; Talisveyberg, K.; Fliter, D.; Kolodny, A.; Weiser, U.; Friedman, E.: Models of memristors for spice simulations. In: IEEE 27th Convention of Electrical Electronics Engineers in Israel (IEEEI), 2012, Nov 2012, pp. 1–5.

  29. Marrakchi, Z.: Exploration and optimization of tree-based FPGA architectures, Ph.D. dissertation, Université Pierre et Marie Curie-Paris VI, (2008)

  30. Sentovich, E.; Singh, K.; Lavagno, L.; Moon, C.; Murgai, R.; Saldanha, A.; Savoj, H.; Stephan, P.; Brayton, R.K.: Sangiovanni-Vincentelli, A.L.: SIS: A System For Sequential Circuit Analysis, University of California, Berkeley, Tech. Rep. UCB/ ERLM92/41, (1992)

  31. Cong, J.; Ding, Y.: Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. In: IEEE Transactions on Computer-Aided Design, vol. 13, no. 1, Jan 1994, pp. 1–12, (1995 Circuit and System Society Best Paper Award in IEEE Transactions on CAD)

  32. Marquart, A.; Betz, V.; Rose, J.: Using cluster-based logic block and timing-driven packing to improve FPGA speed and density. In: Seventh International symposium on FPGA, Monterey, pp. 37–46 (1999)

  33. Kirkpatrick, S.; Jr. C.D.G.; Vecchi2, M.P.: Optimization by simulated annealing. Science, 220(4598), 671–680, (May 1983)

  34. Sechen C., Sangiovanni-Vincentelli A.: The timberwolf placement and routing package. IEEE J. Solid-State Circuits 20(2), 510–522 (1985)

    Article  Google Scholar 

  35. McMurchie, L.; Ebeling, C.: Pathfinder: A negotiation-based performance-driven router for FPGAs. In: ACM International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM Press, pp. 111–117 (1995)

  36. Dijkstra E.W.: A note on two problems in connexion with graphs. Numerische Math. 1(1), 269–271 (1959)

    Article  MathSciNet  MATH  Google Scholar 

  37. Betz, V.; Rose, J.; Marquardt, A.: (eds.) Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA, USA: Kluwer Academic Publishers, (1999)

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Authors and Affiliations

  1. COMSATS Institute of Information Technology, Lahore, Pakistan

    M. Hassan Aslam, Umer Farooq, M. Naeem Awais & Naeem Shehzad

  2. Information Technology University, Lahore, Pakistan

    M. Khurram Bhatti

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  1. M. Hassan Aslam
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  2. Umer Farooq
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  3. M. Naeem Awais
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  4. M. Khurram Bhatti
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  5. Naeem Shehzad
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Correspondence to M. Hassan Aslam.

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Aslam, M.H., Farooq, U., Awais, M.N. et al. Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor-Transistor Hybrid FPGA Architecture. Arab J Sci Eng 41, 3035–3049 (2016). https://doi.org/10.1007/s13369-016-2068-8

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  • DOI: https://doi.org/10.1007/s13369-016-2068-8

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