Abstract
Memory block occupies most of the integrated chip area and an improvement in memory cell performance will enhance the overall system performance. Ever increasing levels of on-chip integration of static random access memory (SRAM) increases leakage and degrades cell stability. In this paper a low-power multimodal switch (LPMS) power gating structure is proposed to minimize leakage and improve data stability in SRAM cell. The proposed design provides maximum of 91% reduction in leakage power and 23.5% reduction in dynamic power over conventional methods. Read and write margins are enhanced by 4.7 and 7.5% respectively. Proposed LPMS technique offers good leakage reduction and stability even under different operating parameter variations.
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Kavitha, M., Govindaraj, T. Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell. Arab J Sci Eng 41, 2945–2955 (2016). https://doi.org/10.1007/s13369-016-2047-0
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DOI: https://doi.org/10.1007/s13369-016-2047-0