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Arabian Journal for Science and Engineering

, Volume 39, Issue 6, pp 4875–4890 | Cite as

Minimization of CNTFET Ternary Combinational Circuits Using Negation of Literals Technique

  • V. Sridevi
  • T. Jayanthy
Research Article - Electrical Engineering

Abstract

A multi-threshold design can be achieved by employing carbon nanotubes (CNTs) with different diameters, as the threshold voltage of the carbon nanotube field effect transistor (CNTFET) depends on the diameter of the CNT. In this paper, this feature is exploited to design ternary logic circuits for achieving improved performance. We presented new design for CNTFET-based ternary combinational circuits such as half adder, full adder, half subtractor, full subtractor and comparator using negation of literals technique. Extensive simulation results using Synopsis HSPICE simulator demonstrate that using new technique 5–145 times improvement in power delay product can be achieved with reduced gate count compared to the existing ternary–binary combinational gate design.

Keywords

Adder Chiralities CNTFET Comparator Decoder Hspice Multi-valued logic Power delay product Subtractor Ternary 

Abbreviations

MVL

Multi-valued logic

CNT

Carbon nanotube

CNTFET

Carbon nanotube field effect transistor

STI

Simple ternary inverter

PTI

Positive ternary inverter

NTI

Negative ternary inverter

FA

Full adder

HA

Half adder

PDP

Power delay product

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Copyright information

© King Fahd University of Petroleum and Minerals 2014

Authors and Affiliations

  1. 1.Sathyabama UniversityChennaiIndia
  2. 2.Panimalar Institute of TechnologyChennaiIndia

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