Arabian Journal for Science and Engineering

, Volume 36, Issue 2, pp 259–278 | Cite as

Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

  • Sadiq M. Sait
  • Ali M. Zaidi
  • Mustafa I. Ali
  • Khawar S. Khan
  • Sanaullah Syed
Research Article – Computer Engineering and Computer Science


Combinatorial optimization problems are generally NP hard problems that require large run-times when solved using iterative heuristics. Parallelization using distributed or shared memory computing clusters thus becomes a natural choice to speed up the execution times of such problems. In this paper, several parallel schemes based on an asynchronous multiple-Markov-chain (AMMC) model are explored to parallelize simulated annealing (SA), used for solving a multiobjective VLSI cell placement problem. The different parallel schemes are investigated based on the speedups and solution qualities achieved on an inexpensive cluster of workstations. The problem requires the optimization of conflicting objectives (interconnect wire-length, power dissipation, and timing performance), and fuzzy logic is used to integrate the costs of these objectives. The goal is to develop effective AMMC-based parallel SA schemes to achieve near linear speedups while maintaining or achieving higher solution qualities in less time and to analyze these parallel schemes against the common critical performance factors.


Asynchronous MMC Parallel SA schemes Multiobjective cell placement Cluster-of-workstations 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Sait SM, Youssef H (1999) Iterative computer algorithms with applications in engineering: solving combinatorial optimization problems. IEEE Computer Society Press, CaliforniaMATHGoogle Scholar
  2. 2.
    Banerjee P (1994) Parallel algorithms for VLSI computer-aided design. Prentice-Hall, Englewood CliffsGoogle Scholar
  3. 3.
    Cung V-D, Martins SL, Riberio CC, Roucairol C (2001) Strategies for the parallel implementation of metaheuristics. In: Essays and surveys in metaheuristics. Kluwer, Dordrecht, pp 263–308Google Scholar
  4. 4.
    Crainic TG, Toulouse M (2003) Parallel strategies for metaheuristics. In: Glover FW, Kochenberger GA (eds) Handbook of metaheuristics, pp 465–514Google Scholar
  5. 5.
    Witte EE, Chamberlain RD, Franklin MA (1991) Parallel SA using speculative execution. IEEE Trans Parallel Distributed Syst 2(4)Google Scholar
  6. 6.
    Lee S-Y, Lee KG (1996) Synchronous and asynchronous parallel simulated annealing with multiple-Markov-chains. IEEE Trans Parallel Distributed Syst 7(10): 993–1008CrossRefGoogle Scholar
  7. 7.
    Chandy J, Kim S, Ramkumar B, Parkes S, Bannerjee P (1997) An evaluation of parallel simulated annealing strategies withapplication to standard cell placement. IEEE Trans Comput Aided Des Integrated Circuits Syst 16(4): 398–410CrossRefGoogle Scholar
  8. 8.
    Sait SM, Zaidi AM, Ali MI (2006) Asynchronous MMC based parallel SA schemes for multiobjective standard cell placement. In: Proceedings of 2006 international symposium in circuits and systems (ISCAS), pp 4615–4618Google Scholar
  9. 9.
    Toulouse M, Crainic TG (2002) State-of-the-art handbook in metaheuristics. In: Parallel strategies for metaheuristics. Kluwer Academic Publishers, DordrechtGoogle Scholar
  10. 10.
    Kravitz SA, Rutenbar RA (1987) Placement by simulated annealing on a multiprocessor. IEEE Trans Comput Aided Des 6(4): 534–549CrossRefGoogle Scholar
  11. 11.
    Jayaraman R, Darema F (1988) Error tolerance in parallel simulated annealing techniques. In: Proceedings of the 1988 IEEE international conference on computer design: VLSI in computers and processors, pp 545–548Google Scholar
  12. 12.
    Durand MD, White SR (2000) Trading accuracy for speed in parallel simulated annealing with simultaneous moves. High Perform Comput Oper Res 26(1): 135–150MATHMathSciNetGoogle Scholar
  13. 13.
    Banerjee P, Jones MH, Sargent JS (1990) Parallel simulated annealing algorithms for standard cell placement on hypercube multiprocessors. IEEE Trans Parallel Distributed Syst 1: 91–106CrossRefGoogle Scholar
  14. 14.
    Casotto A, Romeo F, Sangiovanni-Vincentelli A (1987) A parallel simulated annealing algorithm for the placement of macro-cells. IEEE Trans Comput Aided Des CAD-6: 838–847CrossRefGoogle Scholar
  15. 15.
    Sun WJ, Sechen C (1994) A loosely coupled parallel algorithm for standard cell placement. In: Digest of papers, International conference on computer-aided design, pp 137–144Google Scholar
  16. 16.
    Sait SM, Youssef H, Hussain A (1999) Fuzzy simulated evolution algorithm for multiobjective optimization of VLSI placement. In: IEEE congress on evolutionary computation, July 1999, pp 91–97Google Scholar
  17. 17.
    Devadas S, Malik S (1995) A survey of optimization techniques targeting low power VLSI circuits. In: 32nd ACM/IEEE design automation conferenceGoogle Scholar
  18. 18.
    Chandrakasan A, Sheng T, Brodersen RW (1992) Low power CMOS digital design. J Solid State Circuits 4(27): 473–484CrossRefGoogle Scholar
  19. 19.
    Yager RR (1988) On ordered weighted averaging aggregation operators in multicriteria decision making. IEEE Trans Syst Man Cybern 18(1)Google Scholar
  20. 20.
    Konishi K, Taki K, Kimura K (1995) Temperature parallel simulated annealing algorithm and its evaluation. Trans Inf Process Soc Jpn 36(4): 797–807Google Scholar
  21. 21.
    Ingber L (1993) Simulated annealing: practice versus theory. J Math Comput Model 18(11): 29–57MATHCrossRefMathSciNetGoogle Scholar

Copyright information

© King Fahd University of Petroleum and Minerals 2011

Authors and Affiliations

  • Sadiq M. Sait
    • 1
  • Ali M. Zaidi
    • 1
  • Mustafa I. Ali
    • 1
  • Khawar S. Khan
    • 1
  • Sanaullah Syed
    • 1
  1. 1.College of Computer Sciences and EngineeringKing Fahd University of Petroleum & MineralsDhahranSaudi Arabia

Personalised recommendations