Skip to main content

Advertisement

SpringerLink
Log in

Optimizing cache energy efficiency in multicore power system simulations

  • Original Paper
  • Published:
Energy Systems Aims and scope Submit manuscript

Abstract

Due to recent trends in computer chip design and architecture, the power consumption of computing systems is increasing. Further, with increasing number of cores on a single chip, the size of cache is also increasing and hence, their contribution in overall processor power consumption has become significant. As computing systems become ubiquitous, their excessive power consumption is likely to increase the demands of electricity, thus increasing the level of stress on power systems. In this paper, we propose an approach for reducing cache energy consumption in power system dynamic simulations which are computationally intensive. Our approach is based on the observation that there exists large intra- and inter-program variation in cache resource demand in simulation of different contingencies. Thus, using decay cache technique, we dynamically turn off the cache blocks to save cache energy. In multicore systems, the requirements of meeting worst-case cache demand leads to over-provisioning of resources and hence, saving cache energy is even more important in multicore systems. Hence, we evaluate energy savings in the context of both dual-core and quad-core processors. We simulate several contingencies of different power systems using time domain simulation. Further, we explore the opportunity of dynamically saving cache energy by using a computer architecture simulator and simulate dual-core and quad-core processor configurations. The results show that our technique is effective in saving cache energy and also keeps the loss in performance minimal.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5

Similar content being viewed by others

Notes

  1. Leakage energy (also called static energy) consumption refers to the energy consumed in any component such as a cache, even when there is no activity.

  2. Instruction traces record the sequences of memory references performed by the program.

References

  1. http://www.top500.org. Accessed 20 Dec 2012

  2. http://snipersim.org. Accessed 20 Dec 2012

  3. http://electrica.uc3m.es/pablole/new_england.html (2013). Accessed 20 Dec 2012

  4. CACTI 5.3: http://quid.hpl.hp.com:9081/cacti/. Accessed 20 Dec 2012

  5. Abella, J., González, A., Vera, X., O’Boyle, M.: IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. 2(1), 55–77 (2005). doi:10.1145/1061267.1061271

  6. Albonesi, D.: Selective cache ways: on-demand cache resource allocation. Microarchitecture, 1999. In: Proceedings. of the 32nd Annual International Symposium on MICRO-32, pp. 248–259 (1999)

  7. Carlson, T.E., Heirman, W., Eeckhout, L.: Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulations. In: International Conference for High Performance Computing, Networking, Storage and Analysis (SC) (2011)

  8. Chang, J., Sohi, G.: Cooperative cache partitioning for chip multiprocessors. In: Proceedings of the 21st annual international conference on Supercomputing. ACM, New York, pp. 242–252 (2007)

  9. Feng, W., Cameron, K.: The green500 list: encouraging sustainable supercomputing. Computer 40(12), 50–55 (2007)

    Article  Google Scholar 

  10. Flautner, K., Kim, N., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: simple techniques for reducing leakage power. In: 29th Annual International Symposium on Computer Architecture (ISCA), pp. 148–157 (2002)

  11. Fu, C.: High-speed extended-term time-domain simulation for online cascading analysis of power systemalysis of power system. Ph.D. thesis (2011)

  12. Hanson, H., Hrishikesh, M., Agarwal, V., Keckler, S., Burger, D.: Static energy reduction techniques for microprocessor caches. IEEE Trans. VLSI Sys. 11(3), 303–313 (2003). doi:10.1109/TVLSI.2003.812370

    Article  Google Scholar 

  13. Hennessy, J., Patterson, D.: Computer architecture: a quantitative approach. Morgan Kaufmann, Menlo Park (2011)

  14. Homayoun, H., et al.: Adaptive techniques for leakage power management in L2 cache peripheral circuits. In: ICCD, pp. 563–569 (2008)

  15. Huh, J., Burger, D., Keckler, S.: Exploring the design space of future cmps. In: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, 2001. IEEE, USA, pp. 199–210 (2001)

  16. Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: 28th annual international symposium on Computer architecture (ISCA), pp. 240–251 (2001)

  17. Kaxiras, S., Martonosi, M.: Computer architecture techniques for power-efficiency. Synth. Lect. Comput. Archit. 3(1), 1–207 (2008)

    Article  Google Scholar 

  18. Khaitan, S., McCalley, J., Chen, Q.: Multifrontal solver for online power system time-domain simulation. IEEE Trans. Power Sys. 23(4), 1727–1737 (2008)

    Article  Google Scholar 

  19. Khaitan, S.K., et al.: High performance computing for power system dynamic simulation. In: High Performance Computing in Power and Energy Systems, Power Systems, pp. 43–69 (2013)

  20. Li, J., Martinez, J.: Power-performance implications of thread-level parallelism on chip multiprocessors. In: ISPASS 2005 of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005. IEEE, USA, pp. 124–134 (2005)

  21. Li, Y., et al.: State-preserving vs. non-state-preserving leakage control in caches. In: DATE (2004)

  22. Mittal, A., Hazra, J., Jain, N., Goyal, V., Seetharam, D., Sabharwal, Y.: Real time contingency analysis for power grids. In: Euro-Par 2011 Parallel Processing. pp. 303–315 (2011)

  23. Mittal, S.: A survey of architectural techniques for DRAM power management. Int. J. High Perform. Sys. Archit. 4(2), 110–119 (2012)

    Article  Google Scholar 

  24. Mittal, S., Zhang, Z.: Palette: A cache leakage energy saving technique for green computing. In: HPC: Transition Towards Exascale Processing, Advances in Parallel Computing. IOS Press, USA (2013)

  25. Mittal, S., et al.: EnCache: Improving cache energy efficiency using a software-controlled profiling cache. In: IEEE EIT (2012)

  26. Mittal, S., et al.: CASHIER: A Cache Energy Saving Technique for QoS Systems. In: IEEE 26th VLSI Design Conference (2013)

  27. Monchiero, M., Canal, R., González, A.: Design space exploration for multicore architectures: a power/performance/thermal view. In: Proceedings of the 20th annual international conference on Supercomputing. ACM, New York, pp. 177–186 (2006)

  28. Naveh, A., et al.: Power and thermal management in the Intel Core Duo processor. Intel Tech. J. (2006)

  29. Patel, C., Ranganathan, P.: Enterprise power and cooling. In: ASPLOS Tutorial (2006)

  30. Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.: Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: International Symposium on Low power electronics and design (ISLPED), pp. 90–95 (2000). doi:10.1109/LPE.2000.155259

  31. Qureshi, M., Patt, Y.: Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, pp. 423–432 (2006)

  32. Sanchez, D., Kozyrakis, C.: Vantage: scalable and efficient fine-grain cache partitioning. ACM SIGARCH Comput. Archit. News 39(3), 57–68 (2011)

    Article  Google Scholar 

  33. Tullsen, D., Brown, J.: Handling long-latency loads in a simultaneous multithreading processor. In: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, IEEE Computer Society, pp. 318–327 (2001)

  34. Yang, S.H., Falsafi, B., Powell, M.D., Roy, K., Vijaykumar, T.N.: An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches. In: 7th International Symposium on High-Performance Computer Architecture (HPCA) (2001)

  35. Zhou, H., Toburen, M., Rotenberg, E., Conte, T.: Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Sys. 2(3), 347–372 (2003). doi:10.1145/860176.860181

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering, Iowa State University, Ames, IA, USA

    Siddhartha Kumar Khaitan & James D. McCalley

Authors
  1. Siddhartha Kumar Khaitan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. James D. McCalley
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Siddhartha Kumar Khaitan.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Khaitan, S.K., McCalley, J.D. Optimizing cache energy efficiency in multicore power system simulations. Energy Syst 5, 163–177 (2014). https://doi.org/10.1007/s12667-013-0090-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12667-013-0090-4

Keywords

Search

Navigation