Abstract
Composite Galois field multiplication is one of the most important and complex nonlinear arithmetic unit in symmetric cipher algorithms. However, current hardware implementations are hard to maintain high performance and flexibility. Based on reconfigurable technology, we propose a flexible architecture of composite Galois field multiplication (RCGFM) and dedicated instructions of composite Galois filed multiplication (ICGFM) over \(GF((2^{n} )^{m} )\), where \(n = 8,m = 1,2,3,4\). The RCGFM adopts a serial–parallel mixed structure, which can achieve different Galois field multiplications with good parallelism and scalability. By extending the \(x^{k} B\) multiplications of serial chain, where \(k = 1,2,3\), the RCGFM can concurrently support the composite Galois filed multiplications with higher orders, such as \(GF((2^{8} )^{m} )\), where \(m \ge 5,m \in {\mathbb{Z}}^{ + }\). Moreover, in order to reduce the instruction overhead of target symmetric crypto processor, the ICGFM is specially designed, which is composed of operation and configuration instructions for \(x^{k} B\) and \(A \times B\) over \(GF((2^{n} )^{m} )\). The ICGFM can be applied to RCGFM structure efficiently and flexibly by configuring the corresponding parameters. The experimental results show that under 0.18 µm CMOS technology, the maximum clock frequency is 625 MHz, while the area of circuit is 11.2 kilo gates. Compared with current researches, the RCGFM structure can improve the throughput rate more than a factor of 1.36x–9.19x, when normalized to the same technology and per kilo gates, the technology-scaled throughput rate increases more than a factor of 1.25x–4.4x, while the area overhead does not increase significantly. In addition, the ICGFM can reduce 1–2 orders of magnitude the number of instructions compared with other works. At last, the reconfigurable architecture we proposed supports different composite Galois field multiplications over \(GF((2^{n} )^{m} )\) with more flexibility and efficiency.
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Acknowledgements
This work was supported in part by the NNSF of China (No. 61704136); China Postdoctoral Science Foundation (No. 2018M631163); Shaanxi Postdoctoral Research Project Foundation (No. 2017BSHEDZZ29); the Fundamental Research Funds for the Central Universities (No. Z201805200); Guangdong Province Key R&D project (No. 2019B010154002); Key Research and Development Plan of Shaanxi Province (No. 2019ZDLGY03-07-01); Basic Research Foundation of Engineering University of PAP of China (No. WJY201916); Youth Research Project of Yan’an University of China (No. YDQ2018-05); Innovation and Entrepreneurship Training Program for College Students of China (No. D2017136).
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Su, Y., Yang, BL., Yang, C. et al. High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor. J Ambient Intell Human Comput 12, 7727–7743 (2021). https://doi.org/10.1007/s12652-020-02497-8
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DOI: https://doi.org/10.1007/s12652-020-02497-8