Abstract
In the present work a precise but simple empirical model for single gate nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFET is proposed. The threshold voltage is calculated by solving the two-dimensional (2D) Poisson equation under befitting boundary conditions incorporating short-channel effects, the effect of strain, strained-silicon thin film thickness, and gate work function. The proposed empirical model provides results comparable with those obtained from 2D device simulation thereby establishing the extent of accuracy of our present model. The empirical model so developed correctly exhibits that the threshold voltage is reduced with the increase of strain in the silicon thin film. We have investigated, herewith our proposed model, the influences of various device parameters like: strain (with minute amount of carbon and significant amount of Ge), strained-silicon thin-film thickness and gate work function on the threshold voltage. The extent of equivalent Ge content enhances the performance of the proposed MOSFET in terms of better speed because of the carrier mobility enhancement due to addition of carbon atoms.
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S H Oh, D Monroe and J M Hergenrother IEEE Electron Device Lett. 21 445 (2000)
G V Reddy and M J Kumar IEEE Trans. Nanotechnol. 4 280 (2005)
M M Ahmed IEEE Trans. Electron Devices 48 830 (2001)
G Baccarani and S Reggiani IEEE Trans. Electron Devices 46 1656 (1999)
A Kargar and R Ghayour Indian J. Phys. 85 369 (2011)
T E Whall and E H C Parker Rev. Article J. Phys. D 31 1397 (1998)
J Walczak and B Majkusiak J. Telecommun. Inf. Technol. 3 84 (2007)
C K Maity et al., Def. Sci. J. 50 299 (2000)
G K Daalpati et al., IEEE Trans. Electron Devices 53 1142 (2006)
F Schaffler Rev. Article Semicond. Sci. Technol. 12 1515 (1997)
N Sugii, S Yamaguchi and K Nakagawa Semicond. Sci. Technol. 16 155 (2001)
A Biswas and P K Basu Semicond. Sci. Technol. 16 947 (2001)
S C Jain, H J Oscent, B Dietrich and H Rucker Semicond. Sci. Technol. 10 1289 (1995)
G S Kar, S Maikap, S K Ray, S K Banerjee and N B Chakrabarti Semicond. Sci. Technol. 17 471 (2002)
W Zhou, F Luo, Z Yu, X Zhao and B Li Indian J. Phys. 85 607 (2011)
M J Kumar, V Venkataraman and S Nawal IEEE Trans. Electron Devices 53 2500 (2006)
J Y Wei, S Maikap, M H Lee, C C Lee and C W Liu Solid-State Electronics 50 109 (2006)
K K Young IEEE Trans. Electron Devices 36 399 (1989)
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Basu, S., Sarkar, S.K. & Sarkar, S.K. Exploring novel characteristics of strain compensated SiGeC nanoscale MOSFET. Indian J Phys 87, 333–338 (2013). https://doi.org/10.1007/s12648-012-0233-9
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DOI: https://doi.org/10.1007/s12648-012-0233-9