This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of power, delay, temperature, voltage, noise and corner variations. Power consumption and delay is computed and analysed for wide range of temperature and 40.78–95.5% saving in power delay product is obtained with the same. Quantification of bias voltage variation effect and process corners to find the effectiveness of the proposed design are examined and it is found to be performing consistently as compared with other techniques. Later on bouncing noise analysis is done for the valuation of noise in the circuit. Comparison of power delay product, transistor count and clock phase is done with several previously reported designs. Comprehensive simulation in cadence using 90 nm technology, shows that the proposed design vanquish conventional and other previously reported dynamic circuit design techniques in all aspect of circuit performance. Further, an arithmetic logic unit for measurement using sensors is implemented as a prolongation of the proposed dynamic circuit design technique.
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The authors duly acknowledge with gratitude the support from ministry of Electronics and information technology, Govt. of India, New Delhi, for providing facilities for research, through special Manpower Development Program at National Institute of Technology, Delhi, India.
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Verma, P., Pandey, V.S., Sharma, A.K. et al. Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique. MAPAN 33, 405–416 (2018). https://doi.org/10.1007/s12647-018-0275-3
- Low power
- Dynamic logic
- Bouncing noise