Skip to main content

Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique


This paper targets to present energy efficient high speed true single phase clock dynamic circuit design technique, utilizing a novel body biasing tuner. The threshold voltage is controlled dynamically by dint of a novel body bias tuner so that performance of the circuit is enhanced in terms of power, delay, temperature, voltage, noise and corner variations. Power consumption and delay is computed and analysed for wide range of temperature and 40.78–95.5% saving in power delay product is obtained with the same. Quantification of bias voltage variation effect and process corners to find the effectiveness of the proposed design are examined and it is found to be performing consistently as compared with other techniques. Later on bouncing noise analysis is done for the valuation of noise in the circuit. Comparison of power delay product, transistor count and clock phase is done with several previously reported designs. Comprehensive simulation in cadence using 90 nm technology, shows that the proposed design vanquish conventional and other previously reported dynamic circuit design techniques in all aspect of circuit performance. Further, an arithmetic logic unit for measurement using sensors is implemented as a prolongation of the proposed dynamic circuit design technique.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13


  1. [1]

    M. Orshansky, L. Milor, P. Chen, K. Keutzer and C. Hu, Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits, IEEE Trans. Comput. Aided Des. Circuits Syst., 21 (2002) 544–553.

    Article  Google Scholar 

  2. [2]

    X. Ouyang, C.N. B. Milor and R.F.W. Pease, High-throughput mapping of short range spatial variations using active electrical metrology, IEEE Trans. Semicond. Manuf., 15 (2002) 108–117.

    Article  Google Scholar 

  3. [3]

    M. Helmy and A. Raouf, Manual/automated capacitance box using Micro-Controller technique, MAPAN-J. Metrol. Soc. India, 26 (2011) 105–113.

    Google Scholar 

  4. [4]

    H. Gopalakrishnan and W.T. Shiue, Leakage power reduction using self bias transistor in VLSI circuits, Micro. & electron devices IEEE workshop, Boise, USA (2004), 71–74.

    Google Scholar 

  5. [5]

    Y. Ji-Ren, I. Karlsson and C. Svensson, A ture single-phase-clock dynamic CMOS circuit technique, IEEE J. Solid-State Circuits, 22 (1987) 899–901.

    ADS  Article  Google Scholar 

  6. [6]

    L. Wang, R.K. Krishnamurthyt, K. Soumyanatht and N.R. Shanbhag, An energy efficient leakage tolerant dynamic circuit technique, IEEE conference, Urbana (2002), 221–225.

  7. [7]

    D. Radhakrishnan, Low-voltage low-power CMOS full adder, IEE Proc.-Circuits Dev. Syst., 148 (2001) 19–24.

    Article  Google Scholar 

  8. [8]

    J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, Prentice–Hall of India Private Limited, 2004.

    Google Scholar 

  9. [9]

    R. Kar, D. Mandal, G. Khetan, S. Meruva, Low power VLSI circuit implementation using mixed static CMOS and domino logic with delay elements, IEEE-SCOReD, Malaysia (2011) 370–374.

    Google Scholar 

  10. [10]

    Hamid M. Meimand and K. Roy, Diode-footed domino, a leakage-tolerant high fan-in dynamic circuit design style, IEEE Trans. Circuits Syst., 51 (2004) 495-503.

    Article  Google Scholar 

  11. [11]

    F. Frustaci, P. Corsonello, S. Perri and G. Cocorullo, High performance noise tolerant circuit techniques for CMOS dynamic logic, IET Circuits Dev. Syst., 2 (2008) 537–548.

    Article  Google Scholar 

  12. [12]

    F. Moradi et. al, Domino logic design for high performance and leakage tolerant applications,” Integr. VLSI J., 46 (2013) 247–254.

    Article  Google Scholar 

  13. [13]

    A. Dadoria et. al, A novel high-performance leakage-tolerant, wide fan-in domino logic circuit in deep-submicron technology, Sci. Res., 6 (2015) 103–111.

  14. [14]

    M. Manzoor et. al., Various techniques to overcome noise in dynamic CMOS logic, Int. J. Sci. Technol., 22 (2016) 1–7.

    Google Scholar 

  15. [15]

    N. Weste, K. Eshraghian and Addison-Wesley, Principles of CMOS VLSI Design, Pearson, 1994, 343–346.

  16. [16]

    S.M. Kang, Y. Leblebici and C.W. Kim, CMOS digital integrated circuits analysis & design, TMH (2017) 383–387.

  17. [17]

    B. Razavi, TSPC logic—a circuit for all seasons, IEEE Solid-State Circuits Maga., 8 (2016)10–13.

    Google Scholar 

  18. [18]

    P. Larsson and C. Svensson, Impact of clock slope on true single phase clocked (TSPC) CMOS circuit, IEEE J. Solid State Circuits, 29 (1994) 723–726.

    ADS  Article  Google Scholar 

  19. [19]

    K.H. Cheng and Y.C.Huang, The non-full voltage swing TSPC (NSTSPC) logic design, IEEE AP-ASIC, Korea (2000) 37–40.

    Google Scholar 

  20. [20]

    S. Kim, C.H. Ziesler and M.C. Papaeftymiou, A true single phase energy recovery multiplier, IEEE Trans. VLSI Syst., 11 (2003) 194–207.

    Article  Google Scholar 

  21. [21]

    F.M. Hernandez, M.L. Aranda and V. Champac, Noise tolerance improvement in dynamic CMOS logic circuits, IEE Proc-Circuits Dev. Syst., 153 (2006) 565–573.

    Article  Google Scholar 

  22. [22]

    A. Asati, Chandrashekhar, A high speed pipelined dynamic circuit implementation using modified TSPC logic design style with improved performance, Int. J. Recent Trends Eng., 1 (2009) 24–27.

    Google Scholar 

  23. [23]

    P. Sharma, R. Chandel and S. Sarkar, Noise tolerant technique in super and sub-threshold region of TSPC logic, Special Issue of IJCA-ICEICE, 5 (2011) 25–28.

    Google Scholar 

  24. [24]

    A. Mitra, Design and analysis of low power high speed 1-bit full adder cell based on TSPC logic with multithreshold CMOS, world academy of science, Eng. Technol., 8 (2014) 1–4.

    Google Scholar 

  25. [25]

    R. Rastogi and S. Pandey, Implementing low power dynamic adder in MTCMOS technology, IEEE-ICECS, Coimbatore (2015) 782–786.

    Google Scholar 

  26. [26]

    S.-Y. Ahn and K. Cho, Small-swing domino logic based on twist-connected transistors, Electron. Lett., 50 (2014) 1054–1056.

    Article  Google Scholar 

  27. [27]

    H. Xue, S. Ren, Low power-delay-product dynamic CMOS circuit design techniques, IET-Electron. Lett., 53 (2017) 302–304.

    Article  Google Scholar 

  28. [28]

    I-Chyn Wey et al., Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique, Wiley Int. J. Circ. Theory Appl., 43 (2015) 854–865.

    Article  Google Scholar 

  29. [29]

    D. Saikia, P.K. Boruah and U. Sarma, A sensor network to monitor process parameters of fermentation and drying in black tea production, MAPAN-J. Metrol. Soc. India, 30 (2015) 211–219.

    Google Scholar 

  30. [30]

    G. Lentka, Scalable measurement system for multiple impedance gas sensors, MAPAN-J. Metrol. Soc. India, 3 (2017) 223–228.

    Google Scholar 

  31. [31]

    A. Srivastava and C. Zang, An adaptive body bias generator for low voltage CMOS VLSI circuits, Int. J. Distrib. Sensor Netw., 4 (2008) 213–222.

    Article  Google Scholar 

Download references


The authors duly acknowledge with gratitude the support from ministry of Electronics and information technology, Govt. of India, New Delhi, for providing facilities for research, through special Manpower Development Program at National Institute of Technology, Delhi, India.

Author information



Corresponding author

Correspondence to Preeti Verma.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Verma, P., Pandey, V.S., Sharma, A.K. et al. Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique. MAPAN 33, 405–416 (2018).

Download citation


  • Low power
  • Delay
  • Dynamic logic
  • TSPC
  • Bouncing noise