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Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications

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Abstract

This paper presents the design and analysis of a vertical dopingless double gate junctionless field-effect transistor (VDL-DG-JLFET) on a silicon-on-insulator (SOI) substrate, utilizing the charge plasma concept. 2D TCAD numerical simulations have been carried out to evaluate and compare switching and analog/ RF performance parameters with a vertical double gate junctionless accumulation field-effect transistor (VDG-JAMFET). The results demonstrate that the VDL-DG-JLFET exhibits superior gate control and delivers substantial enhancements in critical parameters such as drive current (ID), reduction of drain-induced barriers (DIBL), subthreshold swing (SS), and the on-current to off-current ratio (ION/IOFF) when juxtaposed with the VDG-JAMFET. Additionally, the VDL-DG-JLFET demonstrates improved transconductance (gm), cut-off frequency (fT), and maximum oscillation frequency (fmax) compared to the VDG-JAMFET. These findings collectively highlight the superior attributes of the VDL-DG-JLFET in comparison to the VDG-JAMFET, reinforcing its potential for advanced electronic applications.

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Funding

The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

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Authors and Affiliations

  1. Department of Electronics & Communication Engineering, Dev Bhoomi Uttarakhand University, Dehradun, 248007, Uttarakhand, India

    Aanchal Garg

  2. Department of Electronics & Communication Engineering, School of Engineering and Technology, University Institute of Engineering & Technology, Babasaheb Bhimrao Ambedkar University, Lucknow, 226025, Uttar Pradesh, India

    Balraj Singh

  3. Department of Electronics and Communication Engineering, G B Pant Institute of Engineering and Technology, Pauri Garhwal, Uttarakhand, 246194, India

    Yashvir Singh

Authors
  1. Aanchal Garg
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  2. Balraj Singh
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  3. Yashvir Singh
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Contributions

All authors participated in shaping and conceptualizing the study. Aanchal Garg conducted material preparation, TCAD simulation, and analysis. Balraj Singh and Yashvir Singh were responsible for the formal analysis and investigation of the simulated results. Aanchal Garg initially drafted the manuscript, which was then revised and edited by Balraj Singh and Yashvir Singh.

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Correspondence to Balraj Singh.

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Garg, A., Singh, B. & Singh, Y. Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications. Silicon 16, 2719–2728 (2024). https://doi.org/10.1007/s12633-024-02873-5

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