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A new Vertical C-shaped Silicon Channel Nanosheet FET with Stacked High-K Dielectrics for Low Power Applications

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Abstract

Vertical Nanosheet Transistors serves as a potential substitute for the Nanowire and FinFET architecture at advanced technology nodes on account of higher drive current and superior control of short channel effects. In this article, a novel analysis of various stacked high-K dielectrics in n-type Vertical C-shaped Silicon Channel Nanosheet Field Effect Transistor (nVCNFET) is implemented. In-depth analysis is done on the effects of stacked high-K dielectrics on nVCNFET device performance and short channel effects. The nVCNFET with optimized gate oxide stack of Al2O3-TiO2 exhibits a remarkable current ratio of 3.2 × 1016, which is 107 times efficient over the reported Vertical Nanosheet FETs (NSFET) up to date. The Device performance and scaling compatibility of nVCNFET for sub-10 nm and 5 nm technology nodes are demonstrated to certify the device’s reliability. On the contrary, the proposed nVCNFET maintains ideal Subthreshold Swing (< 60 mV/decade) and yields 60% lesser DIBL value (8 mV/V) over the other Silicon-NSFETs. This concludes nVCNFET, a befitting candidate for low power and Dynamic Random Access Memory (DRAM) applications.

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Acknowledgements

The authors acknowledge Karunya Institute of Technology and Sciences, Coimbatore, India for providing the support and facility to carry out this research work.

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The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Karunya Institute of Technology and Sciences, Coimbatore, India

    Angelin Delighta A, S. Angen Franklin & D. Nirmal

  2. Department of Bio-Medical Engineering, Karunya Institute of Technology and Sciences, Coimbatore, India

    Binola K Jebalin. I.V

  3. Department of Electronics and Communication Engineering, SR University, Warangal, Telangana, India

    J. Ajayan

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  1. Angelin Delighta A
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  2. Binola K Jebalin. I.V
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  3. J. Ajayan
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Contributions

Miss. Angelin Delighta A and Dr. D. Nirmal have role in Conceptualization, Methodology, Writing Original Draft, Validation and Investigation. Dr. Binola K Jebalin. I.V, Mr. S. Angen Franklin and Dr. J. Ajayan have the credits to Software, Formal analysis, Resources, Data Curation, Writing Review and Editing.

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Correspondence to D. Nirmal.

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A, A.D., I.V, B.K.J., Ajayan, J. et al. A new Vertical C-shaped Silicon Channel Nanosheet FET with Stacked High-K Dielectrics for Low Power Applications. Silicon 16, 2659–2670 (2024). https://doi.org/10.1007/s12633-024-02871-7

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