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Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs

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Abstract

In this article, a physics-based 2-D analytical model for electrical characteristics such as electric field, surface potential, and drain current of source pocket hetero-dielectric double-gate tunnel FET (SP-HD-DG-TFET) is proposed to simultaneously increase the drain current and immune the subthreshold swing (SS). The presented structure of the device consists of a source pocket of highly n+-doped Silicon with a horizontally stacked gate-oxide structure of HfO2/SiO2. Poisson’s equation has been discussed in the channel region by applying the parabolic approximation technique and appropriate boundary conditions. The expression of the electric field has been developed using the channel potential model. Analytically integration of band-to-band tunneling generation rate over the channel thickness yields the drain current expression. The device’s performances of SP-HD-DG-TFETs using the suggested model have been found better in terms of V-I characteristics, ION/IOFF, and SS as compared with hetero-diegetic double gate TFET (HD-DG-TFET), high-k TFET and conventional DG-TFET. The suggested model’s output has been compared to simulation results produced by the SILVACO ATLAS TCAD tool and found to be in good accordance between them.

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References

  1. Choi WY, Park B-G, Lee JD, Liu T-JK (2007) Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745

    Article  ADS  CAS  Google Scholar 

  2. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373):329–337

    Article  ADS  CAS  PubMed  Google Scholar 

  3. Bhuwalka KK, Schulze J, Eisele I (2005) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans Electron Devices 52(5):909–917

    Article  ADS  CAS  Google Scholar 

  4. Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G (2007) Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett 91(5):053102–1–053102–3

  5. Krishnamohan T, Kim D, Raghunathan S, Saraswat K (2008) Double gate strained-ge heterostructure tunneling FET (TFET) With record high drive currents and 60mV/dec subthreshold slope. IEDM Tech Dig, pp 1–3

  6. Leonelli D, Vandoren A, Rooyackers R, Verhulst AS, De Gendt S, Heyns MM, Groeseneken G (2010) Performance enhancement in multi-gate tunneling field effect transistors by scaling the fin-width. Jpn J Appl Phys 49(4S):04DC10

  7. Tomioka K, Fukui T (2014) Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length. Appl Phys Lett 104(2):073507–073514

    Article  ADS  Google Scholar 

  8. Beneventi GB, Gnani E, Gnudi A, Reggiani S, Baccarani G (2014) Dual-metal-gate InAs tunnel FET with enhanced turn-on steepness and high on-current. IEEE Trans Electron Devices 61(3):776–784

    Article  ADS  CAS  Google Scholar 

  9. Hou Y-T, Li M-F, Low T, Wong D-LK (2004) Metal gate work function engineering on gate leakage of MOSFETs. IEEE Trans Electron Devices 51(11):1783–1789

    Article  ADS  CAS  Google Scholar 

  10. Patel N, Ramesha A, Mahapatra S (2008) Drive current boosting of n-type tunnel FET with strained SiGe layer at source. Microelectron J 39(12):1671–1677

    Article  CAS  Google Scholar 

  11. Kim SH, Agarwal S, Jacobson ZA, Matheu P, Hu C, Liu T-JK (2010) Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett 31(10):1107–1109

    Article  ADS  CAS  Google Scholar 

  12. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with a high-κ gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  ADS  CAS  Google Scholar 

  13. Kavi KK, Dewvedi A, Mishra RA (2022) Performance improvement of TFET using gate drain overlap structure with heterojunction. In: 2022 IEEE 9th Uttar Pradesh section international conference on electrical, electronics and computer engineering (UPCON). IEEE, pp 1–5

  14. Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans Electron Devices 57(9):2317–2319

    Article  ADS  Google Scholar 

  15. Kavi KK, Tripathi S, Mishra RA (2022) Simulation and performance analysis of gate source overlapped duel material double gate tunnel field effect transistor with SiO2/HfO2 Stacked-gate oxide structure. Advances in VLSI, communication, and signal processing: select proceedings of VCAS 2021. Singapore: Springer Nature Singapore, pp 635–643

  16. Verhulst AS, Sorée B, Leonelli D, Vandenberghe GW, Groeseneken G (2010) Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J Appl Phys 107(2):024518–1–024518–6

  17. Pan A, Chen S, Chui CO (2013) Electrostatic modeling and insights regarding multigate lateral tunneling transistors. IEEE Trans Electron Devices 60(9):2712–2720

    Article  ADS  Google Scholar 

  18. Vishnoi R, Kumar MJ (2014) A pseudo-2D-analytical model of dual material gate-all-around nanowire tunneling FET. IEEE Trans Electron Devices 61(7):2264–2270

    Article  ADS  Google Scholar 

  19. Bardon MG et al (2010) Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans Electron Devices 57: 827–834

  20. Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410

    Article  ADS  CAS  Google Scholar 

  21. Jain P, Prabhat V, Ghosh B (2015) Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material. J Comput Electron 14:537–542

    Article  CAS  Google Scholar 

  22. Vishnoi R, Kumar MJ (2014) Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport. IEEE Trans Electron Devices 61(6):1936–1942

    Article  ADS  CAS  Google Scholar 

  23. Prabhat V, Dutta AK (2016) Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs. IEEE Trans Electron Devices 63(5):2190–2196

    Article  ADS  Google Scholar 

  24. Samuel TSA, Balamurugan NB, Sibitha S, Saranya R, Vanisri D (2013) Analytical modeling and simulation of dual material gate tunnel field effect transistors. J Electr Eng Technol 8(6). The Korean Institute of Electrical Engineers, pp 1481–1486

  25. Goswami R, Bhowmick B, Baishya S (2016) Physics-based surface potential, electric field and drain current model of a δp+ Si1–xGex gate–drain underlap nanoscale n-TFET. Int J Electron 103(9):1566–1579. https://doi.org/10.1080/00207217.2016.1138514

    Article  CAS  Google Scholar 

  26. Jhaveri R, Nagavarapu V, Jason CS (2011) Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans Electron Devices 58:80–86

    Article  ADS  CAS  Google Scholar 

  27. Chang HY, Adams B, Chien PY, Li J, Jason CS (2013) Improved subthreshold and output characteristics of source-pocket Si Tunnel FET by the application of laser annealing. IEEE Trans Electron Devices 60(1):92–96

    Article  ADS  CAS  Google Scholar 

  28. Kavi KK, Tripathi S, Mishra RA, Kumar S (2022) Design, simulation, and work function trade for dc and analog/RF performance enhancement in dual material hetero dielectric double gate tunnel FET. Silicon 14(15):10101–10113

  29. Mamidala SR, Dawit BA (2015) Dopingless PNPN tunnel FET with improved performance: design and analysis. Superlattices Microstruct 82:430–437

    Article  Google Scholar 

  30. Wang P, Zhuang Y, Li C, Jiang Z, Liu Y (2016) Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket. Microelectron Reliab. https://doi.org/10.1016/j.microrel.2015.09.014

  31. Talukdar J, Rawat G, Mummaneni K (2020) A novel extended source TFET with δp+- SiGe layer. Silicon 12:2273–2281

    Article  Google Scholar 

  32. Lu H, Lu B, Zhang Y, Zhang Y, Lv Z (2019) Drain current model for double gate tunnel-FETs with InAs/Si heterojunction and source-pocket architecture. Nanomaterials 9:181. https://doi.org/10.3390/nano9020181

  33. Sharma V, Kumar S, Talukdar J, Mummaneni K, Rawat G (2022) Source Pocket engineered hetero gate dielectric SOI Tunnel FET with improved performance. Mater Sci Semicond Process 143:106541

  34. ATLAS (2019) 2-D Device Simulator. SILVACO Int, Santa Clara, CA, USA

  35. Talukdar J, Rawat G, Mummaneni K (2021) dielectrically modulated single and double gate tunnel FET based biosensors for enhanced sensitivity. IEEE Sens J 21(23):26566–26573

    Article  ADS  CAS  Google Scholar 

  36. Kumar S, Goel E, Singh K, Singh B, Kumar M, Jit S (2016) A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/High- k stacked gate-oxide structure. IEEE Trans Electron Devices 60(8):3291–3299

    Article  ADS  Google Scholar 

  37. Kumar S, Singh K, Chander S, Goel E, Singh PK, Baral K, Singh B, Jit S (2017) 2-D analytical drain current model of double-gate heterojunction TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices 65:331–338

  38. Kumar S, Singh K, Baral K, Singh PK, Jit S (2021) 2-D analytical model for electrical characteristics of dual metal heterogeneous gate dielectric double-gate TFETs with localized interface charges. Silicon 13:2519–2527

  39. Kane EO (1960) Zener tunneling in semiconductors. J Phys Chem Solids 12(2):181–188

    Article  ADS  CAS  Google Scholar 

  40. Dash S, Mishra GP (2015) A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattices Microstructure. 86:211–220

    Article  ADS  CAS  Google Scholar 

  41. Gholizadeh M, Hosseini SE (2014) A 2-D analytical model for double gate tunnel FETs. IEEE Trans Electron Devices 61(5):1494–1500

    Article  ADS  Google Scholar 

  42. Choi WY, Lee HK (2016) Demonstration of hetero-gate-dielectric tunnelling field effect transistors (HG TFETs), Nano Convergence (ISSN: 2196–5404) 3(1):13

  43. Dhiman P, Kavi KK, Ratnesh RK, Kumar A (2023) Controlling the ambipolar current by using graded drain doped TFET. In: 2023 International conference on device intelligence, computing and communication technologies, (DICCT). IEEE, pp 249–252

  44. Dhiman P, Kavi KK, Ratnesh RK, Kumar A (2023) Design and analysis of a source pocket dual material hetero dielectric double gate TFET for improved performance. 2023 international conference on device intelligence, computing and communication technologies, (DICCT), pp 1–5

  45. Kavi KK, Kiroula K, Kumar M, Dwivedi A, Mishra RA (2022) Performance evaluation of dual material double gate TFET based biosensor. 2022 IEEE students conference on engineering and systems (SCES), pp 1–5

  46. Gupta V, Awasthi H, Kumar N, Pandey AK, Gupta A (2022) A novel approach to model threshold voltage and subthreshold current of graded-doped junctionless-gate-all-around (GD-JL-GAA) MOSFETs. Silicon 14:2989–2997

  47. Gupta A, Rai A, Kumar N, Sigroha D, Kishore A, Pathak V, Rahman ZU (2022) A novel approach to investigate the impact of hetero-high-K gate stack on SiGe junctionless gate-all-around (JL-GAA) MOSFET. Silicon 14:1005–1012

  48. Lu H, Lu B, Zhang Y, Zhang Y, Lv Z (2019) Drain current model for double gate tunnel-FETs with InAs/Si heterojunction and source-pocket architecture. Nanomaterials 9(2):181

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Acknowledgements

We thank the New Research Sholar VLSI Lab of ECED, MNNIT Allahabad, Prayagraj, India, for providing resources and Dr. Abhinaw Gupta for the fruitful suggestion and discussion.

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This work was not financially supported.

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All authors participated in the writing of the manuscript for significant intellectual content and gave their final approval of the version to be published. Kavindra Kumar Kavi has done the simulations and modelling work which made significant contributions to the conception and design, data acquisition, data analysis, and interpretation. Shweta Tripathi prepared all the figures 1-11. R.A Mishra has made sufficient contributions to the work to accept accountability for relevant portions of the content. Sanjay Kumar wrote the entire mathematical modelling equations in throughout the manuscript. All authors reviewed and approved the final manuscript.

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Correspondence to Kavindra Kumar Kavi.

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Kavi, K.K., Tripathi, S., Mishra, R.A. et al. Analytical Modeling for Electrical Characteristics of Source Pocket-Based Hetero Dielectric Double-Gate TFETs. Silicon 16, 1273–1282 (2024). https://doi.org/10.1007/s12633-023-02754-3

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