Skip to main content
SpringerLink
Log in

Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The impact of the work function modulation (WFM) in sub-20nm strained silicon channel double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power arithmetic circuit applications. A 14nm double gate junctionless transistor (DGJLT) followed by formation of strained channel and WFM in metal gate is designed on sentaurus TCAD, where 2-D mixed mode simulation at supply voltage (VDD) = 0.8V is performed to configure a hybrid full adder (HFA). From the analyses, the WFM based HFA is found to be superior by providing the least power, delay and PDP. The variability of HFAs is also tested as a function of the physical parameters like VDD, load capacitor, and temperature.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

Authors declare that the manuscript contains all the data.

Code Availability

Not applicable.

References

  1. Bazzazi A, Eskafi B (2010) Design and implementation of full adder cell with the gdi technique based on 0.18 μ m cmos technology. In: International multiconference of engineers and computer scientists (IMES), vol 2. Citeseer

  2. Bui HT, Wang Y, Jiang Y (2002) Design and analysis of low-power 10-transistor full adders using novel xor-xnor gates. IEEE Trans Circ Syst II: Analog and Digit Signal Process 49(1):25–30

    Google Scholar 

  3. Chandrakasan AP, Sheng S, Brodersen RW (1992) Low-power cmos digital design. IEICE Trans Electron 75(4):371–382

    Google Scholar 

  4. Chang CH, Gu J, Zhang M (2005) A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(6):686–695

    Article  Google Scholar 

  5. Chen Z, Xiao Y, Tang M, Xiong Y, Huang J, Li J, Gu X, Zhou Y (2012) Surface-potential-based drain current model for long-channel junctionless double-gate mosfets. IEEE Trans Electron Devices 59(12):3292–3298

    Article  CAS  Google Scholar 

  6. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’neill B, Blake A, White M et al (2010) Nanowire transistors without junctions. Nature Nanotechnol 5 (3):225–229

    Article  CAS  Google Scholar 

  7. Duarte JP, Choi SJ, Choi YK (2011a) A full-range drain current model for double-gate junctionless transistors. IEEE Trans Electron Devices 58(12):4219–4225

    Article  Google Scholar 

  8. Duarte JP, Choi SJ, Moon DI, Choi YK (2011b) Simple analytical bulk current model for long-channel double-gate junctionless transistors. IEEE Electron Device Lett 32(6):704–706

    Article  Google Scholar 

  9. Edgar LJ (1930) Method and apparatus for controlling electric currents. US Patent 1,745,175

  10. Fischetti M, Gamiz F, Hänsch W (2002) On the enhanced electron mobility in strained-silicon inversion layers. J Appl Phys 92(12):7320–7324

    Article  CAS  Google Scholar 

  11. Goel S, Kumar A, Bayoumi MA (2006) Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-cmos logic style. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(12):1309–1321

    Article  Google Scholar 

  12. Gundapaneni S, Ganguly S, Kottantharayil A (2011) Bulk planar junctionless transistor (bpjlt): an attractive device alternative for scaling. IEEE Electron Device Lett 32(3):261–263

    Article  CAS  Google Scholar 

  13. Han MH, Chang CY, Chen HB, Cheng YC, Wu YC (2013a) Device and circuit performance estimation of junctionless bulk finfets. IEEE Trans Electron Devices 60(6):1807–1813

    Article  Google Scholar 

  14. Han MH, Chang CY, Jhan YR, Wu JJ, Chen HB, Cheng YC, Wu YC (2013b) Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis. IEEE Electron Device Lett 34(2):157–159

    Article  Google Scholar 

  15. Jeon DY, Park S, Mouis M, Barraud S, Kim GT, Ghibaudo G (2013) A new method for the extraction of flat-band voltage and doping concentration in tri-gate junctionless transistors. Solid State Electron 81:113–118

    Article  CAS  Google Scholar 

  16. Kandpal J, Tomar A, Agarwal M, Sharma KK (2020) High-speed hybrid-logic full adder using high-performance 10-t xor–xnor cell. IEEE Trans Very Large Scale Integr (VLSI) Syst 28(6):1413–1422

    Article  Google Scholar 

  17. Kumar R, Bala S, Kumar A (2022) Study and analysis of advanced 3d multi-gate junctionless transistors. Silicon 14(3):1053–1067

    Article  CAS  Google Scholar 

  18. Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511

    Article  Google Scholar 

  19. Martin CG, Oruklu E (2014) Performance evaluation of finfet pass-transistor full adders with bsim-cmg model. In: IEEE 57th international midwest symposium on circuits and systems (MWSCAS). IEEE, 917–920

  20. Oya T, Asai T, Fukui T, Amemiya Y (2003) A majority-logic device using an irreversible single-electron box. IEEE Trans Nanotechnol 2(1):15–22

    Article  Google Scholar 

  21. Park CH, Ko MD, Kim KH, Baek RH, Sohn CW, Baek CK, Park S, Deen M, Jeong YH, Lee JS (2012) Electrical characteristics of 20-nm junctionless si nanowire transistors. Solid State Electron 73:7–10

    Article  CAS  Google Scholar 

  22. Paz BC, Ávila-Herrera F, Cerdeira A, Pavanello MA (2015) Double-gate junctionless transistor model including short-channel effects. Semicond Sci Technol 30(5):055011

    Article  Google Scholar 

  23. Pokhrel TR, Majumder A (2022) Impact of work function engineering on strained silicon based double gated junction-less transistor. Silicon:1–9

  24. Radhakrishnan D (2001) Low-voltage low-power cmos full adder. IEE Proc Circ Devices Syst 148(1):19–24

    Article  Google Scholar 

  25. Su CJ, Tsai TI, Liou YL, Lin ZM, Lin HC, Chao TS (2011) Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett 32(4):521–523

    Article  CAS  Google Scholar 

  26. Tahrim A, Chin HC, Lim CS, Tan MLP, et al. (2015) Design and performance analysis of 1-bit finfet full adder cells for subthreshold region at 16 nm process technology. J Nanomater:2015

  27. Tirumalasetty VR, Avireni S (2012) Modified level restorers using current sink and current source inverter structures for bbl-pt full adder. Radioengineering 21(4):1279–1286

    Google Scholar 

  28. Trevisoli RD, Doria RT, de Souza M, Das S, Ferain I, Pavanello MA (2012) Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors. IEEE Trans Electron Devices 59(12):3510–3518

    Article  Google Scholar 

  29. Vesterbacka M (1999) A 14-transistor cmos full adder with full voltage-swing nodes. In: IEEE workshop on signal processing systems. SiPS 99. Design and implementation (Cat. No. 99TH8461). IEEE, pp 713–722

  30. Yang M, Oruklu E (2018) Full adder circuit design using lateral gate-all-around (lgaa) fets based on bsim-cmg mode. In: 2018 IEEE 61st international midwest symposium on circuits and systems (MWSCAS). IEEE, pp 420–423

  31. Zimmermann R, Fichtner W, et al. (1997a) Low-power logic styles: cmos versus pass-transistor logic. IEEE J Solid State Circ 32(7):1079–1090

    Article  Google Scholar 

  32. Zimmermann R, Fichtner W, et al. (1997b) Low-power logic styles: cmos versus pass-transistor logic. IEEE J Solid State Circ 32(7):1079–1090

    Article  Google Scholar 

Download references

Acknowledgements

We are grateful to National Institute of Technology Arunachal Pradesh for the financial help to execute this work.

Funding

TEQIP-III, NIT Arunachal Pradesh has funded EDA tool to carry out this work.

Author information

Authors and Affiliations

  1. Integrated Circuit & System Lab, Department of ECE, National Institute of Technology Arunachal Pradesh, Itanagar, 791113, India

    Tika Ram Pokhrel & Alak Majumder

  2. Graphic Era Hill University, Bell Road, Derhadun, 248002, India

    Jyoti Kandpal

Authors
  1. Tika Ram Pokhrel
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jyoti Kandpal
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Alak Majumder
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Tika Ram Pokhrel: Simulation & analysis, device Conceptualization and preparation of the manuscript.

Jyoti Kandpal: Circuit conceptualization & preparation of the manuscript.

Alak Majumder: Finalization of manuscript & guidance.

Corresponding author

Correspondence to Tika Ram Pokhrel.

Ethics declarations

The authors hereby declare the following:

Ethics approval

Not applicable.

Consent to participate

Not Applicable.

Consent for Publication

All authors have agreed to publish the article under Springer Nature.

Conflict of Interests/Competing interests

Not Applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Pokhrel, T.R., Kandpal, J. & Majumder, A. Configuring a Hybrid Full Adder Using Strained-Si Channel DG JLT with Work Function Modulation. Silicon 15, 4513–4519 (2023). https://doi.org/10.1007/s12633-023-02327-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-023-02327-4

Keywords

Search

Navigation