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Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits

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Abstract

This paper deals with an innovative structure of silicon-on-insulator junctionless transistor (SOIJLT) by incorporating a buried metal layer of proper work-function which creates the Schottky junction between device layer and the buried metal layer. The buried metal layer results in perfect volume inversion in OFF-state due to which in comparison to SOIJLT, the off-state current (IOFF) of the proposed buried metal SOIJLT (BMSOIJLT) is significantly reduced. In addition, the short-channel effects such as subthreshold swing (SS) and the drain-induced barrier lowering (DIBL) in the proposed BMSOIJLT are reduced by 40% and 30% respectively over the SOIJLT device. The CMOS digital logic circuits such as inverter, NAND gate and the NOR gate have also been implemented using the mixed-mode device/circuit simulations. Despite due to lower ON-state drive current (ION) and the parasitic capacitances in the proposed BMSOIJLT, the propagation delay in SOIJLT and the proposed BMSOIJLT based logic gates is comparable. Moreover, due to significant reduction in IOFF the static power dissipation in the proposed BMSOIJLT based logic gates is significantly low.

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Authors and Affiliations

  1. Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, 440010, India

    Kaustubh K. Tiple & Ganesh C. Patil

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  1. Kaustubh K. Tiple
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  2. Ganesh C. Patil
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All the authors contributed equally.

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Correspondence to Ganesh C. Patil.

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Tiple, K.K., Patil, G.C. Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits. Silicon 15, 1003–1009 (2023). https://doi.org/10.1007/s12633-022-02080-0

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