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Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units

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Abstract

The design of a 20-FinFET novel full adder (NFA) with a new architecture employing Double Gate-FinFETs is presented in this work. The feature of new topology is, the input carry of full adder has to traverse through single transistor, by which the speed of full adder is enhanced. Carry propagation is a critical factor in determining the speed of multi-bit adders like carry choose adders, carry save adders, and ripple carry adders, hence input carry is chosen above the other two inputs. The proposed NFA eliminates the complex XOR/XNOR functions for the generation of sum and output carry. The power factor is also addressed in the design, which is reduced by employing a NOR topology in the first stage of the complete adder and designing it using FinFETs at 22 nm and low supply voltage. The circuit's different topology is designed so that the number of 'n' and 'p' type FinFETs is balanced. The proposed NFA is designed and extensively simulated at 22 nm by testing its performance with various supply voltages like 0.6 V, 1 V, 1.2 V and 1.5 V using Cadence Virtuoso, ADE, ADEXL design suite. The NFA outperforms the existing full adders by reducing the delay and power dissipation by 23%- 31% and 15%—23% respectively.

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Data availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

The authors would like to express gratitude to Department of EIE, KITS, Warangal, Telangana, India. The authors would also like to thank to Prof. K. Ashoka Reddy, Principal, KITS, Warangal, Telangana, India.

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The author(s) received no financial support for the research, authorship, and/or publication of this article.

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  1. KITS, Warangal, Telangana, India

    Jeevan Battini & Sivani Kosaraju

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  1. Jeevan Battini
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  2. Sivani Kosaraju
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Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by [B. Jeevan] and [K. Sivani]. The first draft of the manuscript was written by [B. Jeevan] and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Jeevan Battini.

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Battini, J., Kosaraju, S. Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units. Silicon 15, 993–1002 (2023). https://doi.org/10.1007/s12633-022-02073-z

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