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Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis

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Abstract

This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO2 which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10−16) and high ION/IOFF ratio (~1011) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as ION/IOFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications.

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Acknowledgments

Raj Kumar acknowledges the UGC, India for the financial assistance and UIET (ECE), Panjab University for providing Lab facility.

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Authors and Affiliations

  1. Chandigarh Engineering College, Landran, Sahibzada Ajit Singh Nagar, Punjab, India

    Shashi Bala, P. N. Hrisheekesha & Harpal Singh

  2. University Institute of Engineering and Technology, Panjab University, Chandigarh, India

    Raj Kumar & Arvind Kumar

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  1. Shashi Bala
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Correspondence to Shashi Bala.

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Bala, S., Kumar, R., Hrisheekesha, P.N. et al. Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis. Silicon 15, 1037–1047 (2023). https://doi.org/10.1007/s12633-022-02071-1

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