Skip to main content
SpringerLink
Log in

A Comprehensive Review on FinFET in Terms of its Device Structure and Performance Matrices

  • Review Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The revolutions made in the CMOS technology are brought up by, continuous downscaling in order to obtain higher density, better performance and low power consumption, causing deleterious Short Channel Effects. Planar MOSFET’s have faced very hard challenges in the nanometer space, when ever the channel 4length happens to be in the same order of magnitude like the depletion-layer widths of drain and the source junctions. Hence, the channel length of the MOSFET’s should be great enough when compared to the sum of drain and source depletion widths in order to eradicate edge effects. Orelse numerous effects would occur. In MOSFET’s as channel Length diminishes the gate loose’s its control on the channel, as it isn’t good from power consumption point of view. MOSFET’s cannot control leakage path, removing leakage current is a path for improvising electrostatic control. A way of achieving it can be done by using a structure with multiple-gates as they allow the scaling of a transistor beyond the MOSFET scaling limit. In this case, the leakage current happens to be in the channel centre and reducing the channel decreases the current. Hence SOI and FINFET structures are used in order to achieve high gate-to-channel capacitance and decreases drain-to-channel capacitance. Another way of improvising the computational power can be done through changing the materials employed during manufacturing. In short, FINFET devices display superior SCE’s behaviour have considerably lower switching times, and higher current density than MOSFET technology. The review has been done on the various structures for performance escalation materials for FINFET structure performance Escalation as well as the various applications in which FINFET’s are used along with the various applications in which FINFET are used, various parameters used to perform RF and Linearity applications are noted.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

Data Availability

Not applicable.

References

  1. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–287

    Article  CAS  Google Scholar 

  2. Orouji AA, Rahimian M (2012) Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism. Curr Appl Phys 12(5):1366–1371

    Article  Google Scholar 

  3. Yeo Y-C, King T-J, Hu C (2003) MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans Electron Devices 50(4):1027–1035

    Article  CAS  Google Scholar 

  4. Ershov M, Liu HC, Li L, Buchanan M, Wasilewski ZR, Jonscher AK (1998) Negative capacitance effect in semiconductor devices. IEEE Trans Electron Devices 45(10):2196–2206

    Article  Google Scholar 

  5. Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8(2):405–410

    Article  CAS  Google Scholar 

  6. Khan AI, Yeung CW, Hu C, Salahuddin S (2011) Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation. In: IEDM Tech. Dig., pp. 11.3.1–11.3.4

  7. George S et al (2016) Device circuit co design of FEFET based logic for low voltage processors. In: Proc. IEEE Comput. Soc. Annu. Symp. VLSI (ISVLSI), pp. 649–654

  8. Boscke TS, Müller J, Brauhaus D, Schroder U, Bottger U (2011) Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors. In: IEDM Tech. Dig., Washington, DC, USA, p. 24.5.1–24.5.4

  9. Jimenez D, Miranda E, Godoy A (2010) Analytic model for the surface potential and drain current in negative capacitance fieldeffect transistors. IEEE Trans Electron Devices 57(10):2405–2409

    Article  Google Scholar 

  10. Sallese J-M, Meyer V (2004) The ferroelectric MOSFET: a selfconsistent quasi-static model and its implications. IEEE Trans Electron Devices 51(12):2145–2153

    Article  CAS  Google Scholar 

  11. Sharma A, Roy K (2017) Design space exploration of hysteresisfree HfZrOx-based negative capacitance FETs. IEEE Electron Device Lett 38(8):1165–1167

    Article  CAS  Google Scholar 

  12. Khan AI, Chatterjee K, Duarte JP, Lu Z, Sachid A, Khandelwal S, Ramesh R, Hu C, Salahuddin S (2016) Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor. IEEE Electron Device Lett 37(1):111–114

    Article  Google Scholar 

  13. Li K-S et al (2015) Sub-60 mV-swing negative-capacitance FinFET without hysteresis. In: IEDM Tech. Dig., Washington, DC, USA, pp. 22.6.1–22.6.4

  14. Dutta T, Pahwa G, Agarwal A, Chauhan YS (2018) Impact of process variations on negative capacitance FinFET devices and circuits. IEEE Electron Device Lett 39(1):147–150

    Article  CAS  Google Scholar 

  15. Lee H-P, Su P (2017) Suppressed fin-LER induced variability in negative capacitance FinFETs. IEEE Electron Device Lett 38(10):1492–1495

    Article  CAS  Google Scholar 

  16. Raskin J-P, Ming Chung T, Kilchytska V, Lederer D, Flandre D (2006) Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization. IEEE Trans Electron Devices 53(5):1088–1095

    Article  CAS  Google Scholar 

  17. Kumar A (Dec. 2016) Analog and RF performance of a multigate FinFET at nano scale. Superlattice Microst 100:1073–1080

    Article  CAS  Google Scholar 

  18. D. Lederer et al (2006) Dependence of FinFET RF performance on fin width In: Top. Meeting Silicon Monolithic Integr. Circuits RF Syst. Dig. Papers, San Diego, CA, USA, p. 4

  19. Saha R, Bhowmick B, Baishya S (2018) Comparative analysis among single material gate, double material gate, and triple material gate FinFETs: RF/analog and digital inverter performance. J Nanoelectron Optoelectron 13(6):803–811

    Article  Google Scholar 

  20. Saha R, Bhowmick B, Baishya S (2018) Temperature effect on RF/analog and linearity parameters in DMG FinFET. Appl Phys A, Solids Surf 124(9):642

    Article  Google Scholar 

  21. Singh R, Aditya K, Parihar SS, Chauhan YS, Vega R, Hook TB, Dixit A (2018) Evaluation of 10-nm bulk FinFET RF performance conventional versus NC-FinFET. IEEE Electron Device Lett 39(8):1246–1249

    Article  CAS  Google Scholar 

  22. Mueller S, Mueller J, Singh A, Riedel S, Sundqvist J, Schroeder U, Mikolajick T (2012) Incipient ferroelectricity in al-doped HfO2 thin films. Adv Funct Mater 22(11):2412–2417

    Article  CAS  Google Scholar 

  23. Teja P, Sinha SK, Durgesh A (2020) Comparison of MOSFET, MESFET, FinFET and SOI-FinFET. Int J Emerg Technol Innov Res 7(11):1155–1160 ISSN:2349–5162

    Google Scholar 

  24. Lines ME, Glass AM (1979) Principles and Applications of Ferroelectrics and Related Materials. Oxford Univ. Press, Oxford ch. 3

    Google Scholar 

  25. Starkov A, Starkov I (Mar. 2014) Asymptotic description of the time and temperature hysteresis in the framework of landau-khalatnikov equation. Ferroelectrics 461(1):50–60

    Article  CAS  Google Scholar 

  26. Böscke TS, Müller J, Bräuhaus D, Schröder U, Böttger U (2011) Ferroelectricity in hafnium oxide thin films. Appl Phys Lett 99(10):102903

    Article  Google Scholar 

  27. Tenbroek BM, Lee MSL, Redman-White W, Bunyan JT, Uren MJ (1996) Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques. IEEE Trans Electron Devices 43(12):2240–2248

    Article  Google Scholar 

  28. Narang R, Saxena M, Gupta RS, Gupta M (2013) Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans Nanotechnol 12(6):951–957

    Article  CAS  Google Scholar 

  29. Sharma D, Vishvakarma SK (2015) Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron J 46(8):731–739

    Article  CAS  Google Scholar 

  30. Panda DK, Amarnath G, Lenka TR (2018) Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms and its comparison [J]. J Semicond 39(7):074001

    Article  Google Scholar 

  31. Panda DK, Lenka TR (2018) Compact thermal noise model for enhancement mode N-polar GaN MOS-HEMT including 2DEG density solution with two sub-bands. IET Circuits Devices Syst 12(6):810–816

    Article  Google Scholar 

  32. Ghosh P, Haldar S, Gupta RS, Gupta M (Dec. 2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans Electron Devices 59(12):3263–3268

    Article  Google Scholar 

  33. Lazzaz A, Bousbahi K, Ghamnia M (2021) Modeling and Simulation of DG SOI N FinFET 10 nm using Hafnium Oxide. 2021 IEEE 21st International Conference on Nanotechnology (NANO), pp. 177–180

  34. Bindu Madhavi K, Tripathi SL (2020) Strategic Review on Different Materials for FinFET Structure Performance Optimization. IOP Conference Series: Materials Science and Engineering, issn: 1757899X

  35. Kumar SP, Agrawal A, Chaujar R, Gupta RS, Gupta M (2011) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron Reliab 51(3):587–596

    Article  CAS  Google Scholar 

  36. Kim T-W (2020) Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications. Electronics 29(9):29

    Article  Google Scholar 

  37. Mendiratta N (2020) Suman Lata Tripathi “a review on performance comparison of advanced MOSFET structures below 45nm technology node” journal of semiconductor. IOP science 41:1–10

    Google Scholar 

  38. Convertino C, Zota C, Schmid H, Caimi D, Sousa M, Moselund K, Czornomaz L (2019) InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities. Materials 12(87):87

    CAS  Google Scholar 

  39. Sehgal HD, Pratap Y (2020) Comparative Analysis of Junctionless FinFET and Inverted Mode FinFET as Phosphine (PH3) Gas Sensor. 5th International Conference on Devices, Circuits and Systems (ICDCS)

  40. Tiwari R, Parihar N, Thakor K A 3-D TCAD Framework for NBTI Part I: Implementation Details and FinFET Channel Material Impact. 0018–9383 © 2019 IEEE

  41. Tripathi SL, Saxena S (2019) Asymmetric gated Ge-Si0.7Ge0.3 nHTFET and pHTFET for steep subthreshold Characteristics. Int J Microstruct Mater Prop 14:497

    CAS  Google Scholar 

  42. Alfred Kirubaraj A, Senith S, Nisha Malini G, Jesintha, Jino Ramson SR (2019) Exploration Of NFinfet On Various Gate Materials In 22nm And 20nm Technology. Int J Sci Technol Res 8(09)

  43. Tripathi SL (2019) Low Power Ultra-small Ge-SixGe1-x nJLTFET and pJLTFET Characterization and Implementation as CMOS Inverter. WSC Indian Science congress

  44. Zhao C, Xiang J (2019) Atomic Layer Deposition (ALD) of Metal Gates for CMOS. Appl Sci 9:2388

    Article  CAS  Google Scholar 

  45. Bailey S et al (2019) A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16nm FinFET Instance. IEEE J Solid State Circuits 54(10):2786–2801

    Article  Google Scholar 

  46. Sriram SR, Bindu B (2019) A physics- based 3-D potential and threshold voltage model for undoped triple-gate FinFET with interface trapped charges. J Comput Electron 18:37–45

    Article  Google Scholar 

  47. Bassi M, Tripathi SL, Verma S (2019) Analysis and Design of high-K Material Nanowire Transistor for Improved Performance. IEEE IEMCON, Vancouver, BC Canada, pp. 0613–0618

  48. Convertino C, Zota C, Sant S, Eltes F, Sousa M, Caimi D, Schenk A, Czornomaz L (2018) InGaAs-on-Insulator FinFETs with Reduced Off-Current and Record Performance. IEEE

  49. Netsu S, Hellenbrand M, Zota CB, Miyamoto Y, Lind E (2018) A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-Gate MOSFETs. IEEE J Electron Devices Soc 6:408–412

    Article  CAS  Google Scholar 

  50. Saha R, Baishya S, Bhowmick B (2018) 3D analytical modeling of surface potential, threshold voltage, and sub threshold swing in dual-material-gate (DMG) SOI FinFETs. J Comput Electron 17:153–162

    Article  CAS  Google Scholar 

  51. Uemura T, Lee S, Monga U, Choi J, Lee S, Pae S (2018) Technology Scaling Trend of Soft Error Rate in Flip-Flops in 1×1\times nm Bulk FinFET Technology. IEEE Trans Nucl Sci 65(6):1255–1263

    Article  CAS  Google Scholar 

  52. Rashed M et al (2018) Design and Technology Co-Optimization for exploring Power, Performance, Area and Manufacturability Trade-offs in Advanced FDSOI and FinFET Technologies. 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, pp. 89–90

  53. Vijayalakshmi V, Mohan Kumar Naik B (2018) Design and Modelling of 6T FinFET SRAM in 18nm. 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, 2018, pp. 208–211

  54. Uemura T et al (2018) Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit. IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. P-SE.1–1-P-SE.1–4

  55. Sagong HC et al (2018) Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability. IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 121–122

  56. Hiblot G et al (2018) Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices. 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, pp. 122–124

  57. Jalali MS et al (2018) A 4-Lane 1.25-to- 28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, pp. 106–108

  58. Srinivasan V, Le Tuai S, Lee T (2018) F2: FinFETs & FDSOI — A mixed signal circuit designer's perspective," IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 505–507

  59. Golonzka O et al (2018) MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology. 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 18.1.1–18.1.4

  60. Kundu D, Guin S, NagaJyothi G, Sridevi S (2018) High Speed FinFET Traff Comparator Based Function Generator, 2018 International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC), Chennai, pp. 414–418

  61. Gong H et al (Jan. 2018) Scaling Effects on Single-Event Transients in InGaAs FinFETs. IEEE Trans Nucl Sci 65(1):296–303

    Article  CAS  Google Scholar 

  62. Maurya RK, Bhowmick B (2021) Review of FinFET Devices and Perspective on Circuit Design Challenges. Silicon Journal. https://doi.org/10.1007/s12633-021-01366-z ISSN: 18769918

  63. Jaisawal RK, Rathore S, Kondekar PN, Yadav S, Awadhiya B, Upadhyay P, Bagga N (2022) Assessing the analog/{RF} and linearity performances of {FinFET} using high threshold voltage techniques; Semiconductor Science and Technology, Research, pp. 055010

  64. Choi K et al (2021) Reliability Characterization on Advanced FinFET Technology. 2021 IEEE International Interconnect Technology Conference (IITC), 2021, pp. 1–3

Download references

Acknowledgments

The authors acknowledge VIT-AP university for providing the necessary facilities for carrying out the research work.

Funding

Not applicable

Author information

Authors and Affiliations

  1. School of Electronics, VIT-AP University, Amaravati, Andhra Pradesh, 522237, India

    M. Nomitha Reddy & Deepak Kumar Panda

Authors
  1. M. Nomitha Reddy
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Deepak Kumar Panda
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Ms. Nomitha has done the Compressive review . Dr. Deepak has done the necessary editing and paper writing.

Corresponding author

Correspondence to Deepak Kumar Panda.

Ethics declarations

The manuscript is prepared as per the ethical standard of the journal.

Conflict of Interest

The authors declare that they have no conflict of interest.

Consent to Participate

Not applicable.

Consent for Publication

The authors have given Consent for Publication as per the journal policy.

Code Availability

Not applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Reddy, M.N., Panda, D.K. A Comprehensive Review on FinFET in Terms of its Device Structure and Performance Matrices. Silicon 14, 12015–12030 (2022). https://doi.org/10.1007/s12633-022-01929-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-01929-8

Keywords

Search

Navigation