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Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET Implemented in Verilog-A for Circuit Simulation

Abstract

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.

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Data and materials are original work of authors.

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Acknowledgments

Dr. S. B. Rahi (Indian Institute of Technology, Kanpur, India) for their useful suggestions.

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Correspondence to Billel Smaani.

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Smaani, B., Rahi, S.B. & Labiod, S. Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET Implemented in Verilog-A for Circuit Simulation. Silicon (2022). https://doi.org/10.1007/s12633-022-01847-9

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  • DOI: https://doi.org/10.1007/s12633-022-01847-9

Keywords

  • Nanowire
  • Junctionless
  • Gate-all-around MOSFET
  • Analytical compact model
  • Verilog-a
  • Digital circuit
  • Analog circuit