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Design and Simulation of Symmetrical Dual Gate on Drain Side with Overlapped and Underlapped Regions of TFET

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Abstract

A unique Symmetrical Dual Metal Gate Extended on drain side with overlapped and underlapped three regions of Tunnel Field Effect Transistor (DG-ED-TFET) have been designed and demonstrated in this work. The DG-ED-TFET device is formed by a nanogap cavity with an extended symmetrical gate on the drain side with three different materials being consisting of Titanium Dioxide (TiO2), Silicon Dioxide (SiO2), and Hafnium Oxide (HfO2). The innovative TFET device is invented by Silvaco TCAD ATLAS with device dimensions of 60 nm and symmetrical Gate length of 10 nm modernizations. The symmetrical Gate with 10 nm innovation is considered with the same work functions in ATLAS. The proposed DG-ED-TFET structure increases the affectability compared to single gate TFET and Dual Material Gate TFET. This device overcome the low Drain Current (ID) limitations of conventional TFETs. Thus, the proposed nanogap cavity Advanced TFET device has good potential to attract Low power applications.

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Acknowledgements

The authors would like thank SRM University for providing necessary computational tools.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Ramapuram, Chennai, Tamil Nadu, 600089, India

    Tallapaneni Naga Swathi & V. Megala

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  1. Tallapaneni Naga Swathi
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  2. V. Megala
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Contributions

Author 1 (Tallapaneni. Naga Swathi) studied,analyzed the DG-ED TFET and wrote the paper and Author 2 (V. Megala) calibrated the DGED TFET results.

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Correspondence to Tallapaneni Naga Swathi.

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Swathi, T.N., Megala, V. Design and Simulation of Symmetrical Dual Gate on Drain Side with Overlapped and Underlapped Regions of TFET. Silicon 15, 337–343 (2023). https://doi.org/10.1007/s12633-022-01809-1

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