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Investigation of Noise Characteristics in Gate-Source Overlap Tunnel Field-Effect Transistor

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Abstract

The analog circuit performance of tunnel field-effect-transistor (TFET) can be improved by implementing the concept of gate-source overlap. This paper investigates the impact of variation in gate-source overlap length on ON current, leakage current, capacitance and noise spectral density. Further the analysis has been carried out by excluding and including the effect of Gaussian traps. As the gate fully overlaps the source region a high ON current of 2.42*10−4 A/μm, low leakage current of 9.61*10−12 A/μm, ION/IOFF ratio of 108, sub-threshold slope (SS) of 37 mV/dec are obtained. The optimised gate-source overlap length is 60 nm as it shows good electrostatic control and the maximum value of ON-current is achieved but the noise spectral density slightly increases for fully overlapped gate-source region.

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References

  1. Sarkar A, Das AK, De S, Sarkar CK (2012) Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J 43(11):873–882

    Article  Google Scholar 

  2. Chander S, Sinha SK, Chaudhury R, Singh A (2021) Ge-source based L-shaped tunnel field effect transistor for low power switching application. Silicon 29

  3. Donaghy D, Hall S, De Groot CH, Kunz VD, Ashburn P (2004) Design of 50-nm vertical MOSFET incorporating a dielectric pocket. IEEE Trans Electron Devices 51(1):158–161

    Article  CAS  Google Scholar 

  4. Pindoo IA, Sinha SK, Chander S (2020) Improvement of electrical characteristics of SiGe source based tunnel FET device. Silicon 13(9):3209–3215

    Article  Google Scholar 

  5. Hu VPH, Lin HH, Lin YK, Hu C (2020) Optimization of negative-capacitance vertical-tunnel FET (NCVT-FET). IEEE Trans Electron Devices 67(6):2593–2599

    Article  CAS  Google Scholar 

  6. Luo Z, Wang H, An N, Zhu Z (2015) A tunnel dielectric-based tunnel FET. IEEE Electron Device Lett 36(9):966–968

    Article  CAS  Google Scholar 

  7. Talukdar J, Rawat G, Mummaneni K (2020) A novel extended source TFET with δp+-SiGe layer. Silicon 12(10):2273–2281

    Article  Google Scholar 

  8. Chandan BV, Dasari S, Yadav S, Sharma D (2018) Approach to suppress ambipolarity and improve RF and linearity performances on ED-tunnel FET. Micro Nano Lett 13(5):684–689

    Article  CAS  Google Scholar 

  9. Joshi T, Singh Y, Singh B (2020) Extended-source double-gate tunnel FET with improved DC and analog/RF performance. IEEE Trans Electron Devices 67(4):1873–1879

    Article  CAS  Google Scholar 

  10. Mitra SK, Goswami R, Bhowmick B (2016) A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter. Superlattice Microst 92:37–51

    Article  CAS  Google Scholar 

  11. Ionescu AM (2018) Negative capacitance gives a positive boost. Nat Nanotechnol 13(1):7–8

    Article  CAS  PubMed  Google Scholar 

  12. Wu C, Huang Q, Zhao Y, Wang J, Wang Y, Huang R (2016) A novel tunnel FET design with stacked source configuration for average subthreshold swing reduction. IEEE Trans Electron Devices 63(12):5072–5076

    Article  CAS  Google Scholar 

  13. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54:1725–1733

    Article  CAS  Google Scholar 

  14. Goswami R, Bhowmick B (2016) An algorithm for extraction of threshold voltage in heterojunction TFETs. IEEE Trans Nanotechnol 16(1):90–93

    Google Scholar 

  15. Huang JZ, Long P, Povolotskyi M, Klimeck G, Rodwell MJ (2016) Scalable GaSb/InAs tunnel FETs with non-uniform body thickness. IEEE Trans Electron Devices 64(1):96–101

    Article  Google Scholar 

  16. Sedighi B, Hu XS, Liu H, Nahas JJ, Niemier M (2015) Analog circuit design using tunnel-FETs. IEEE Trans Circuits Syst I, Reg Papers 62(1):39–48

    Article  Google Scholar 

  17. Agopian PGD, Martino MD, dos Santos SD, Neves FS, Martino JA, Rooyackers R, Vandooren A, Simoen E, Thean AVY, Claeys C (2014) Influence of the source composition on the analog performance parameters of vertical nanowire-TFETs. IEEE Trans. Electron Devices 62(1):16–22

    Article  Google Scholar 

  18. Kim MS, Liu H, Li X, Datta S, Narayanan V (2014) A steepslope tunnel FET based SAR analog-to-digital converter. IEEE Trans Electron Devices 61(11):3661–3667

    Article  CAS  Google Scholar 

  19. Chander S, Sinha SK, Chaudhary R (2021) Comprehensive review on electrical noise analysis of TFET structures. Superlattices & Microstructures

    Google Scholar 

  20. P. G. D. Agopian, J.A. Martino, R. Rooyackers, A. Vandooren, E. Simoen, A. Thean, and C. Claeys, “Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures,” in Proc. Joint Int. EUROSOI Workshop Int. Conf. Ultimate Integr. Silicon, pp. 13–15, 2016

  21. Y. Morita, K. Fukuda, Y. Liu, T. Mori, W. Mizubayashi, H. Fuketa, S. Otsuka, S. Migita, M. Masahara, K. Endo, and H. Ota, “Tunnel FinFET CMOS inverter with very low shortcircuit current for ultralow-power Internet of Things application,” Jpn. J. Appl. Phys., vol. 56, no. 4S, 2017

  22. Li C, Zhao X, Zhuang Y, Yan Z, Guo J, Han R (2018) Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and analog/RF performance enhancement. Superlattice Microst 115:154–167

    Article  CAS  Google Scholar 

  23. Sant S, Schenk A (May 2016) Methods to enhance the performance of InGaAs/InP heterojunction tunnel FETs. IEEE Trans Electron Devices 63(5):2169–2175

    Article  CAS  Google Scholar 

  24. Liu KM, Cheng CP (2020) Investigation on the effects of gate-source overlap/underlap and source doping gradient of n-type Si cylindrical gate-all-around tunnel field-effect transistors. IEEE Trans Nanotechnol 19:382–389

    Article  CAS  Google Scholar 

  25. Neves FS, Agopian PG, Martino JA, Cretu B, Rooyackers R, Vandooren A, Simoen E, Thean AVY, Claeys C (2016) Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source. IEEE Trans Electron Devices 63(4):1658–1665

    Article  CAS  Google Scholar 

  26. Sentaurus Device User Guide, Synopsys Inc.,Version D-2021.0

  27. Chander S, Sinha SK, Kumar S, Singh PK, Baral K, Singh K, Jit S (2017) Temperature analysis of Ge/Si heterojunction SOI-tunnel FET. Superlattice Microst 110:162–170

    Article  CAS  Google Scholar 

  28. Van Der Wel AP, Klumperink EAM, Kolhatkar JS, Hoekstra E, Snoeij MF, Salm C, Wallinga H, Nauta B (2007) Low-frequency noise phenomena in switched MOSFETs. IEEE J Solid State Circuits 42:540–549

    Article  Google Scholar 

  29. Hooge FN (1994) 1/F noise sources. IEEE Trans Electron Devices 41:1926–1935

    Article  CAS  Google Scholar 

  30. Fossum JG, Yang JW, Trivedi VP (2003) Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Device Lett 24(12):745–747

    Article  CAS  Google Scholar 

  31. Kumar S, Yadav DS (2021) Temperature analysis on electrostatics performance parameters of dual metal gate step channel TFET. Appl Physics A 127(5):1–11

    Article  Google Scholar 

  32. Chen S, Liu H, Wang S, Li W, Wang X, Zhao L (2018) Analog/RF performance of t-shape gate dual-source tunnel field-effect transistor. Nanosc. Res. Lett. 13(1):321

    Article  Google Scholar 

  33. Xie H, Liu H, Han T, Li W, Chen S, Wang S (2020) TCAD simulation of a double L-shaped gate tunnel field-effect transistor with a covered source–channel. Micro Nano Letters 15(4):272–276

    Article  CAS  Google Scholar 

  34. Wu SY (1968) Theory of generation-recombination noise in MOS transistors. Solid State Electron 11:25–32

    Article  Google Scholar 

  35. Mookerjea S, Mohata D, Mayer T, Narayanan V, Datta S (2010) Temperature-dependent I-V characteristics of a vertical In0.53Ga0.47As tunnel FET. IEEE Electron Device Lett 31:564–566

    Article  CAS  Google Scholar 

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Acknowledgements

This work is supported by Science and Engineering Research Board (SERB), Department of Science & Technology, Government of India, CRG/2020/006229, dated: 05/04/2021.

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All simulation results are available with authors.

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Government of India, CRG/2020/006229, dated: 05/04/2021.

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Authors and Affiliations

  1. School of Electronic and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

    Sanjeet Kumar Sinha, Sweta Chander & Rekha Chaudhary

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  1. Sanjeet Kumar Sinha
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  2. Sweta Chander
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  3. Rekha Chaudhary
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Correspondence to Sweta Chander.

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Sinha, S.K., Chander, S. & Chaudhary, R. Investigation of Noise Characteristics in Gate-Source Overlap Tunnel Field-Effect Transistor. Silicon 14, 10661–10668 (2022). https://doi.org/10.1007/s12633-022-01806-4

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  • DOI: https://doi.org/10.1007/s12633-022-01806-4

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