Skip to main content
SpringerLink
Log in

Implementation of Advanced Tunnel Field Effect Transistor (DP-TFET) for High Power Switching Applications

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

As the technology advances to the nanoscale, advanced Tunnel Field-Effect Transistors are very prominent as a part of integrated circuits in the present trend. Advanced Tunnel FET devices have many advantages over conventional Metal Oxide Semiconductor Field Effect Transistor and conventional Metal Semiconductor Field Effect Transistor on their various performance parameters. III-V bandgap semiconductors such as Gallium Arsenide (GaAs), Silicon dioxide (SiO2), Silicon Carbide (SiC) for which Gallium Nitride (GaN) semiconductor material has excellent potential to attract drain current characteristics and electrical characteristics of the proposed device as Dual Pocket-TFET by its wideband gap, high electron mobility, high electric field strength, high thermal conductivity. The dual pocket Tunnel FET have many improved performance parameters which include lower Sub-threshold Swing (SS), lower leakage current, Higher ON current, and higher Ion/Ioff ratio. Various architectures of Tunnel FETs have been found in recent submicron technology; however, vertical Gallium Arsenide and Silicon dioxide-based proposed dual pocket tunnel FET devices are suitable in high power applications with their excellent performance parameters.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

The referred papers will be available on request.

References

  1. Kuhn KJ (2012) Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59(7):1813–1828

    Article  CAS  Google Scholar 

  2. Colinge J-P (1986) Subthreshold slope of thin-film SOI MOSFET’s. IEEE Electron Device Lett EDL-7(4):244–246. https://doi.org/10.1109/EDL.1986.26359

    Article  CAS  Google Scholar 

  3. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288. https://doi.org/10.1109/5.915374

    Article  CAS  Google Scholar 

  4. Talukdar J, Mummaneni K (2020) A non-uniform silicon TFET design with dual-material source and compressed drain. Appl Phys A, Solids Surf. 126(1):1–12

    Google Scholar 

  5. Haensch W et al (2006) Silicon CMOS devices beyond scaling. IBM J Res Develop 50(4–5):339–361. https://doi.org/10.1147/rd.504.0339

    Article  CAS  Google Scholar 

  6. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  7. Vijh M, Gupta RS, Pandey S (2019) Investigation of tunnel field effect transistor for biosensing applications. Proc Photon Electromagn Res Symp pp. 229–233.

  8. Zhao Q-T et al (2015) Si nanowire tunnel FETs for energy efficient nanoelectronics. ECS Trans 66(4):69

    Article  CAS  Google Scholar 

  9. Ajay, M. Gupta, R. Narang, and M. Saxena (2016) Analysis of GaSb-InAs gate all around (GAA) p-i-n tunnel FET (TFET) for application as a bio-sensor. Proc IEEE Int Nanoelectron Conf (INEC). pp. 1–2

  10. Esmaeilzadeh H, Blem E, Amant RS, Sankaralingam K, Burger D (2012) Dark silicon and the end of multicore scaling. IEEE Micro 32(3):122–134. https://doi.org/10.1109/MM.2012.17

    Article  Google Scholar 

  11. TCAD Sentaurus Device User’s Manual (2010) Synopsys. Mountain View, CA, USA

    Google Scholar 

  12. F. Mayer et al. (2008) “Impact of SOI, Si1−xGex OI and GeOI substrates on CMOS compatible tunnel FET performance,” in IEDM Tech. Dig. pp. 1–5

  13. M. W. Dashiell, A. T. Kalambur, R. Leeson, K. J. Roe, J. F. Rabolt, and J. Kolodzey. (2002) The electrical effects of DNA as the gate electrode of MOS transistors,” in Proc. IEEE Lester Eastman Conf. High Perform. Devices pp. 259–264.

Download references

Acknowledgements

We deeply acknowledge Taif University for supporting this study through Taif University Researchers Supporting Project Number (TURSP-2020/150), Taif University, Taif, Saudi Arabia

Author information

Authors and Affiliations

  1. Department of Computer Engineering, College of Computers and Information Technology, Taif University, Taif, Saudi Arabia

    Fawaz Alassery

  2. Computer Science Department, King Abdulaziz University, Jeddah, 21589, Saudi Arabia

    Asif Irshad Khan

  3. Research Scholar, Computer Science and Engineering Department, JJT University, Jhunjhunu, Rajasthan, India

    Mahaboob Sharief Shaik

Authors
  1. Fawaz Alassery
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Asif Irshad Khan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mahaboob Sharief Shaik
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Author 1 (Fawaz Alassery) studied the comparative analysis of advanced Tunnel FETs and wrote the paper. Author 2 (Asif Irshad Khan) calibrated the results for applications and wrote the paper. Author 3 (, Mahaboob Sharief Shaik) compared performance parameters with conventional device

Corresponding author

Correspondence to Mahaboob Sharief Shaik.

Ethics declarations

Ethics Approval

The authors declare that they have no known competing financial interest or personal relationships that could have appeared to influence the work reported in this paper.

Consent to Participate

All authors voluntarily agree to participate in this review paper.

Consent for Publication

All authors give the permission to the Journal to publish this review paper

Conflict of Interest

Authors declare no conflict of Interest.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Alassery, F., Khan, A.I. & Shaik, M.S. Implementation of Advanced Tunnel Field Effect Transistor (DP-TFET) for High Power Switching Applications. Silicon 14, 9589–9593 (2022). https://doi.org/10.1007/s12633-021-01647-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-021-01647-7

Keywords

Search

Navigation