Abstract
In present days, the improved performance in nanoscale dimensions is of enormous need than conventional CMOS devices. This paper presents an insight into Trigate FinFET in 5 nm technology using ATLAS 2D simulator. The drain current model based on surface potential calculation is shown to study the performance of tri gate FinFET. The 2D Poisson’s equation is solved for both the gates of tri gate FinFET which results in effects of gate voltage in performance parameters. Different high-K dielectric materials are used in the proposed device and corresponding parameters are calculated to study its behavior in drain current characteristics, electrical parameters, and analog parameters. The On current is increased by 150 % then the existing architectures. The net electric field is increased by a factor of 2. There is a significant increase in Transconductance of the device. The simulated models are verified using Silvaco TCAD in ATLAS simulator.
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Change history
24 September 2022
A Correction to this paper has been published: https://doi.org/10.1007/s12633-022-02133-4
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The authors would like to Thanks the Reviewers for their valuable suggestions to improve the quality of the manuscript.
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Author 1(P.Vijaya): Conceived and design the analysis, Contributed data and analysis tools, and wrote the paper. Author 2 (Rohit Lorenzo): Performed the analysis, Calibrated the results, and wrote the paper.
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Vijaya, P., Lorenzo, R. Improvement of Ion, Electric Field and Transconductance of TriGate FinFET by 5nm Technology. Silicon 14, 7889–7900 (2022). https://doi.org/10.1007/s12633-021-01536-z
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DOI: https://doi.org/10.1007/s12633-021-01536-z