Skip to main content
SpringerLink
Log in

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

The data and material are available within the manuscript.

References

  1. Mead C (1994) Scaling of MOS technology to sub-micrometer feature sizes. Analog Integr Circ Sig Process 6:9–25

    Article  Google Scholar 

  2. Thompson S, Packan P, Bohr M (1998) MOS scaling: transistor challenges for the 21st century. Intel technology journal 3rd quarter

  3. Rai S (2018) Analytical modelling and analysis of spacer induced shallow source/drain extension junction-less double gate (SDE-JLDG) MOSFET incorporating fringing field effects. J Nanoelectron Optoelectron 13(2):168–177

    Article  Google Scholar 

  4. Reddy Bommireddy P, Kumar M, Lee YW, Manne R, Suh Y, Park SH (2021) Prussian blue analogue Co3 (Co (CN) 6) 2 cuboids as an electrode material for high-performance supercapacitor. J Power Sources 513:230521

    Article  Google Scholar 

  5. Awasthi H, Purwar V, Gupta A (2021) Modeling of threshold voltage and subthreshold current of Junctionless Channel-modulated dual-material double-gate (JL-CM-DMDG) MOSFETs. Silicon. https://doi.org/10.1007/s12633-021-01327-6

  6. Gupta, V., Awasthi, H., Kumar, N. et al. (2021) A novel approach to model threshold voltage and subthreshold current of graded-doped Junctionless-gate-all-around (GD-JL-GAA) MOSFETs. Silicon. https://doi.org/10.1007/s12633-021-01084-6

  7. Gupta A, Rai S, Kumar N, Sigroha D, Kishore A, Pathak V, Rahman ZU (2021) A novel approach to investigate the impact of hetero-high-K gate stack on SiGe Junctionless gate-all-around (JL-GAA) MOSFET. Silicon:1–8. https://doi.org/10.1007/s12633-020-00860-0

  8. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4:99–109

    Article  Google Scholar 

  9. Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, New York

    Book  Google Scholar 

  10. Choi WY, Park BG, Lee JD, Liu TJ (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/ dec. IEEE Electron Device Letters 28(8):743–745

    Article  CAS  Google Scholar 

  11. Kumar A, Gupta A, Rai S (2018) Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma-based junctionless transistor. AEU-Int J Electron Commun 95:162–169

    Article  Google Scholar 

  12. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229

    Article  CAS  Google Scholar 

  13. Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511–053512

    Article  Google Scholar 

  14. Rai S (2017) Reliability analysis of junction-less double gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectron J 64:60–68

    Article  Google Scholar 

  15. Rai MK, Gupta A, Rai S (2021) Comparative analysis and study of various leakage reduction techniques for short channel devices in Junctionless transistors: a review and perspective. silicon:1–23. https://doi.org/10.1007/s12633-021-01181-6

  16. Kumari V, Modi N, Saxena M, Member S (2015) Theoretical investigation of dual material Junctionless double gate transistor for analog and digital performance. IEEE Trans Electron Devices 62:2098–2105

    Article  Google Scholar 

  17. Kumar N, Purwar V, Awasthi H, Gupta R, Singh K, Dubey S (2021) Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube junctionless-double gate-all-around (NJL-DGAA) MOSFETs. Electr J 113:105104. https://doi.org/10.1016/j.mejo.2021.105104

    Article  CAS  Google Scholar 

  18. Roy NC, Gupta A, Rai S (2015) Analytical surface potential modeling and simulation of the junction-less double gate (JLDG) MOSFET for ultra-low-power analog/RF circuits. Microelectron J 46(10):916–922

    Article  CAS  Google Scholar 

  19. Gupta A, Singh A, Gupta SK, Rai S (2018) Potential modeling of oxide engineered doping-less dual-material-double-gate Si–Ge MOSFET and its application. J Nanoelectron Optoelectron 13(8):1115–1122

    Article  CAS  Google Scholar 

  20. Bianchi D, Quaglia F, Mazzanti A, Svelto F (2014) Analysis and design of a high voltage integrated class-B amplifier for ultrasound transducers. IEEE Trans Circuit Syst I 61(7):1942–1951

    Google Scholar 

  21. Khan AA, Kumar A (1992) A novel wide-band differential amplifier. IEEE Trans Instrum Meas 41(4):555–559

    Article  Google Scholar 

  22. Samanta J, De BP, Bag B, Maity RK (2012) Comparative study for the delay and power dissipation of CMOS inverter in UDSM range. Int J Soft Comput Eng 1(6):162–167

    Google Scholar 

  23. Rodoni LC, Ellinger F, Jackel H (2004) Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology. Electron Lett 40(20):1251–1252

    Article  CAS  Google Scholar 

  24. Srivastava NA, Priya A, Mishra RA (2019) Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high-density ICs. Appl Phys A 125(8):1–15

    Article  Google Scholar 

  25. ATLAS User’s manual, Silvaco Inc. (2016)

Download references

Acknowledgements

Not Applicable.

Funding

This work did not receive financial support.

Author information

Authors and Affiliations

  1. Department of Electronics Engineering, Rajkiya Engineering College, Sonbhadra, Uttar Pradesh, 231206, India

    Abhinav Gupta

  2. Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, 211004, India

    Manish Kumar Rai & Sanjeev Rai

  3. Department of Applied Science and Humanities, Rajkiya Engineering College, Ambedkar Nagar, Uttar Pradesh, 224122, India

    Amit Kumar Pandey

  4. Department of Technical Education, I.E.T, A.P.J. Abdul Kalam Technical University, Lucknow, Uttar Pradesh, 226027, India

    Digvijay Pandey

Authors
  1. Abhinav Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Manish Kumar Rai
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Amit Kumar Pandey
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Digvijay Pandey
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Sanjeev Rai
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content, and have given final approval of the version to be published. Each author has participated sufficiently in work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.

Corresponding author

Correspondence to Abhinav Gupta.

Ethics declarations

Ethics Approval

The authors declare that all procedures followed were in accordance with the ethical standards.

Consent to Participate

All the authors declare their consent to participate in this research article.

Consent for Publication

All the authors declare their consent for publication of the article on acceptance.

Conflict of Interest

The authors declare that there is no conflict of interest regarding the publication of this paper.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gupta, A., Rai, M.K., Pandey, A.K. et al. A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs. Silicon 14, 7577–7584 (2022). https://doi.org/10.1007/s12633-021-01520-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-021-01520-7

Keywords

Search

Navigation