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Novel Linearly Graded Nanotube Field-Effect Transistors for Improved Analog Performance and Reduced Leakage Current

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Abstract

In present work, a Linearly Graded (LG) work function is studied by considering the binary metal alloy AσB1−σ composition for the gate electrode. A high-k gate stack LG nanotube field-effect transistor (LG-NT-FET) is investigated for improving the analog performance and reduced leakage current. The present paper introduces novelty by adding charge plasma on the drain side while doping the source side in LG-NT-FET. The proposed device has the core gate, which lays inside the channel and drain area. Both the gates, including the inner and outer gates are playing a crucial role to significantly charge the channel of LG-NT-FET. It can significantly reduce the Short Channel Effects (SCEs) also. Evaluating the electrical performance metrics such as drive currents and SCEs of LG-NT-FET reveals that the proposed device can better perform in comparison with single gate silicon-based nanotube field-effect transistors (SG-NT-FETs). The device metrics get further enhanced with the tightened electrostatic control via stacking of the core-shell gate that enabled volume inversion-phase operation. The comparison of the LG-NT-FET with single gate NTFET offered a significant reduction in leakage current (~ 10− 15), rise in \({\boldsymbol{I}}_{\boldsymbol{O}\boldsymbol{N}}/{\boldsymbol{I}}_{\boldsymbol{O}\boldsymbol{F}\boldsymbol{F}}\) ratio (~ 1013), increase in transconductance and cutoff frequency as compared to the single gate SG-NT-FET. These improvements in electrical performance metrics enable the proposed device, LG-NT-FET, as a potential device to enable CMOS scaling criteria beyond the Si-NW-FET. These improvised characteristics make LG-NT-FET a promising device in designing both digitals and analog applications for FETs.

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Acknowledgements

The Authors are thankful to lab member Dr. Beloni, Dr. Kundan, and Chakresh Jain for their technical discussion. One of the Authors would like to thank JNU and UGC NFSC for their continuous scholarship support. The authors are also thankful to Ashutosh Bhardwaj, Professor, Department of Physics and Astrophysics, University of Delhi, for providing access to Silvaco TCAD tool for carring out simulation study of this research work.

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  1. School of Computer and System Science, Jawaharlal Nehru University, New Delhi, India

    Rakesh Kumar & Jitendra Kumar

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  1. Rakesh Kumar
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  2. Jitendra Kumar
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All authors contributed to the design and simulation. Material preparation, data collection, and analysis were performed by Rakesh Kumar. The first draft of the manuscript was written by Rakesh Kumar and all authors commented in previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Rakesh Kumar.

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Kumar, R., Kumar, J. Novel Linearly Graded Nanotube Field-Effect Transistors for Improved Analog Performance and Reduced Leakage Current. Silicon 14, 6271–6278 (2022). https://doi.org/10.1007/s12633-021-01400-0

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