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Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

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Abstract

The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

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Acknowledgements

The authors would like to acknowledge the support received from Microelectronics and MEMS Laboratory, Electrical Engineering Department of IIT Madras for performing the device simulations.

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Authors and Affiliations

  1. Division of Electronics, School of Engineering, Cochin University of Science and Technology, Kochi, India

    Shikha U S, Rekha K James & Anju Pradeep

  2. Department of Electronics Engineering, College of Engineering Poonjar, Kottayam, India

    Jobymol Jacob

Authors
  1. Shikha U S
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  2. Rekha K James
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  3. Jobymol Jacob
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  4. Anju Pradeep
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Contributions

1. Shikha U S: Conceptualization, Data curation, Formal analysis, Methodology, Investigation, Visualization, Writing – original draft

2. Rekha K James: Supervision

3. Jobymol Jacob: Conceptualization, Formal analysis, Validation, Writing – original draft, Writing – review and editing

4. Anju Pradeep: Writing – review and editing

Corresponding author

Correspondence to Shikha U S.

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S, S.U., James, R.K., Jacob, J. et al. Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET. Silicon 14, 6157–6167 (2022). https://doi.org/10.1007/s12633-021-01382-z

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  • DOI: https://doi.org/10.1007/s12633-021-01382-z

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