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Review of FinFET Devices and Perspective on Circuit Design Challenges

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Abstract

In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase. In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below 32nm technology increases the short channel effects (SCE). To improve the concert in low-power VLSI logic circuits and reduced the SCEs, we need enhanced gate controlling over the channel by using multigate technology. Here, we have discussed numerous architecture of FINFET, the threshold voltage (Vth) and supply voltage (Vdd) optimization, optimization of fin configuration, and low power technique for FinFET domino circuits.

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Acknowledgements

The authors acknowledge the Microelectronics Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, India for providing all necessary facilities to carry out the research work.

Funding

Young Faculty Research Fellowship scheme under Digital India Corporation.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India

    Ravindra Kumar Maurya & Brinda Bhowmick

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  1. Ravindra Kumar Maurya
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  2. Brinda Bhowmick
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The first author has written and documented the paper and the second author collected the research material, checked, and modified the technical content.

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Correspondence to Ravindra Kumar Maurya.

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Maurya, R.K., Bhowmick, B. Review of FinFET Devices and Perspective on Circuit Design Challenges. Silicon 14, 5783–5791 (2022). https://doi.org/10.1007/s12633-021-01366-z

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