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Drain Current Modeling of Tunnel FET using Simpson’s Rule

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Abstract

Tunnel Field Effect Transistor can be introduced as an emerging alternate to MOSFET which is energy efficient and can be used in low power applications. Due to the challenge involved in integration of band to band tunneling generation rate, the existing drain current models are inaccurate. A compact analytical model for simple tunnel FET and pnpn tunnel FET is proposed which is highly accurate. The numerical integration of tunneling generation rate in the tunneling region is performed using Simpson’s rule. Integration is done using both Simpson’s 1/3 rule and 3/8 rule and the models are validated against numerical device simulations. The models are compared with existing models and it is observed that the proposed models show excellent agreement with device simulations in the entire region of operation with Simpson’s 3/8 rule exhibiting the maximum accuracy.

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Acknowledgements

This work was supported in part by Department of Science and Technology (DST), Government of India through FIST project under Dy. No: 100/IFD/4185/2013-14 and Centre for Engineering Research and Development (CERD) through seed money project. The acknowledgement is extended to Microelectronics and MEMS Laboratory, Electrical Engineering Department, IIT Madras for providing us with the facility to use the device simulation tools.

Funding

The authors would like to acknowledge the Department of Science and Technology (DST), Government of India for providing improved Science and Technology infrastructure for research work, through FIST project. The authors would also like to thank Centre for Engineering Research and Development (CERD) for the seed money project fund to initiate this research work.

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Authors and Affiliations

  1. Model Engineering College, APJ Abdul Kalam Technological University, Kerala, India

    Arun A V

  2. Department of Applied Science, College of Engineering Poonjar, Kottayam, Kerala, India

    Minu K K

  3. Department of Electronics Engineering, Model Engineering College, Kochi, Kerala, India

    Sreelakshmi P S

  4. Department of Electronics Engineering, College of Engineering Poonjar, Kottayam, Kerala, India

    Jobymol Jacob

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  1. Arun A V
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Contributions

1 Arun A V: Conceptualization, formal analysis, investigation methodology, device simulation, mathematical modeling, validation, writing- original draft.

2 Minu K K: Mathematical Analysis, modeling methodology, writing - review and editing.

3 Sreelekshmi P S: Formal analysis, device simulation, validation

4 Jobymol Jacob: Conceptualization, formal analysis, investigation methodology, device simulation, mathematical modeling, validation, writing- review and editing, supervision.

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Correspondence to Arun A V.

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V, A.A., K, M.K., S, S.P. et al. Drain Current Modeling of Tunnel FET using Simpson’s Rule. Silicon 14, 5931–5939 (2022). https://doi.org/10.1007/s12633-021-01328-5

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  • DOI: https://doi.org/10.1007/s12633-021-01328-5

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