Skip to main content
Log in

Silicon Based Security for Protection Against Hardware Vulnerabilities

  • Short Communication
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

Silicon based embedded devices are susceptible to hardware attacks viz.: side channel attacks and fault injection attacks. Fault injection attack is an emerging field affecting security concerns related to semiconductor industry. An adversary by manipulating hardware vulnerabilities of silicon devices can easily get access to secret information not intended for it. Semiconductor industry needs a solution which is based on detection and mitigation of fault injection attacks since this category of hardware attack proves to be more dangerous due to its trait of easy conduction and less expertise needed for performing such attacks. Detection of attacks is one of the important factors to be considered for hardware engineer to mitigate a number of largest challenges and complexities associated with hardware attacks. Existing detection techniques are complex and require post si calibration which proves to be less efficient system. Also fewer techniques are available which detects both types of voltage fault injection attacks (positive /negative). To address these drawbacks this paper presents novel voltage fault injection detection technique which is based on op-amp circuits and designed using cadence 180nm technology node. Simulated results show detection of both types of voltage fault injection attack viz.: positive and negative. Further efficiency of detector circuit is tested by changing parameters like TW, TF and TP known as glitch width, glitch frequency and glitch period respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Data Availability

Data and other supplement data will be available.

References

  1. Walker-Roberts S, Hammoudeh M, Aldabbas O, Aydin M, Dehghantanha A (2020) Threats on the horizon: Understanding security threats in the era of cyber-physical systems. J Supercomput 76(4):2643–2664

    Article  Google Scholar 

  2. Garg S, Gupta TK (2018) Low power domino logic circuits in deep-submicron technology using CMOS. Eng Sci Technol 21(4):625–38

    Google Scholar 

  3. Bozzato C, Focardi R, Palmarini F (2019) Shaping the glitch: optimizing voltage fault injection attacks. IACR Trans Cryptogr Hardware Embed Syst 28:199–224

    Article  Google Scholar 

  4. Rioja U, Paguada S, Batina L, Armendariz I (2020) The uncertainty of side-channel analysis: A way to leverage from heuristics. arXiv preprint arXiv:2006.12810

  5. Kenjar Z, Frassetto T, Gens D, Franz M, Sadeghi AR (2020) V0LTpwn: Attacking x86 processor integrity from software. In: 29th {USENIX} Security Symposium ({USENIX} Security 20)

  6. Murdock K, Oswald D, Garcia FD, Van Bulck J, Gruss D, Piessens F (2020) Plundervolt: Software-based fault injection attacks against Intel SGX. In: 2020 IEEE Symposium on Security and Privacy (SP)

  7. Deshpande CR. Hardware fault attack detection methods for secure embedded systems (Doctoral dissertation, Virginia Tech)

  8. Guo X, Mukhopadhyay D, Jin C, Karri R (2015) Security analysis of concurrent error detection against differential fault analysis. J Cryptogr Eng 5(3):153–69

    Article  Google Scholar 

  9. Mozaffari-Kermani M, Azarderakhsh R, Aghaie A (2016) Fault detection architectures for post-quantum cryptographic stateless hash-based secure signatures benchmarked on ASIC. ACM Trans Embed Comput Syst (TECS) 16(2):1–9

    Google Scholar 

  10. Ou C, Lam SK, Zhou C, Jiang G, Zhang F (2020) A Lightweight detection algorithm for collision-optimized divide-and-conquer attacks. IEEE Trans Comput

  11. Spruyt A, Milburn A, Chmielewski Å . Fault Injection as an Oscilloscope: Fault Correlation Analysis. IACR Transactions on Cryptographic Hardware and Embedded Systems. 2021:192–216.

  12. Raychowdhury A, Tschanz J, Bowman K, Lu SL, Aseron P, Khellah M, Geuskens B, Tokunaga C, Wilkerson C, Karnik T, De V (2011) Error detection and correction in microprocessor core and memory due to fast dynamic voltage droops. IEEE J Emerging Sel Top Circuits Syst 1(3):208–17

    Article  Google Scholar 

  13. Das S, Tokunaga C, Pant S, Ma WH, Kalaiselvan S, Lai K, Bull DM, Blaauw DT (2008) Razor II: In situ error detection and correction for PVT and SER tolerance. IEEE J Solid State Circuits 44(1):32–48

    Article  Google Scholar 

  14. Shaber MU, inventor; Koninklijke Philips NV (assignee) (2017) Detection of radiation quanta using an optical detector pixel array and pixel cell trigger state sensing circuits. United States patent US 9,677,931

  15. Yanci AG, Pickles S, Arslan T (2008) Detecting voltage glitch attacks on secure devices. In: 2008 Bio-inspired, Learning and Intelligent Systems for Security. IEEE, New York, pp 75–80

  16. Kasim M, Gupta V, Jebin M (2020) Methodology for detecting glitch on clock, reset and CDC path. In: 2020 5th International Conference on Communication and Electronics Systems (ICCES). IEEE, New York, pp 300–304

  17. Kazemi Z, Hely D, Fazeli M, Beroulle V (2020) A review on evaluation and configuration of fault injection attack instruments to design attack resistant MCU-based IoT applications. Electronics 9(7):1153

    Article  Google Scholar 

  18. Gomina K, Rigaud JB, Gendrier P, Candelier P, Tria A (2014) Power supply glitch attacks: Design and evaluation of detection circuits. In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). IEEE, New York, pp 136–141

  19. Borrel N, Fort J (2020) inventors; STMicroelectronics Rousset SAS, assignee. Glitch detection of a DC voltage. United States patent US 10,768,229

Download references

Author information

Authors and Affiliations

Authors

Contributions

Dr Balwinder Singh and Dr Harsimaran Kaur Guided, concepts, Proof read and helped in Implementations Shaminder Kaur: written paper and concept implementation.

Corresponding author

Correspondence to Balwinder Singh.

Ethics declarations

Consent to Participate

All authors given consents for the publication of this material. 

Consent for Publication

All authors given consents for the publication of this material.

Conflict of Interest

The authors declare that they have no conflict of interest.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kaur, S., Singh, B. & Kaur, H. Silicon Based Security for Protection Against Hardware Vulnerabilities. Silicon 14, 2421–2427 (2022). https://doi.org/10.1007/s12633-021-00989-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-021-00989-6

Keywords

Navigation