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Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET

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Abstract

With inherent structural simplicity due to the omission of ultrasteep p-n junctions, the conventional junctionless FET can be used as a barrier-controlled device with low OFF-current in the nanoscale regime. In this work, numerous performance parameters of conventional double-gate junctionless FET namely threshold voltage, OFF-current, ON-current, ON-to-OFF current ratio, and subthreshold slope have been investigated for the range of gate work function from 4.6 eV to 5.6 eV. The performance of conventional double-gate junctionless FET has been further improved with the proposed recessed double-gate junctionless FET using recessed silicon film in the channel region and it has been found that for the gate work function of 5.1 eV (mid-value) the proposed device shows OFF-current of the order of ~ 10− 14 A/µm, ON-to-OFF current ratio of the order of 1010 and subthreshold slope of 65.6 mV/dec as compared to the conventional double-gate junctionless FET. Interestingly, a range of work function values have been found to obtain the optimum performance from the conventional and proposed recessed double-gate junctionless FETs for low power applications. In the work function window, the variations in transconductance and gate-to-source capacitance for both junctionless devices have been illustrated. The impact of different values of the work function of the two gate electrodes for both junctionless devices has also been presented and it is found that the proposed device reflects robustness with nearly constant subthreshold slope.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Thapar Institute of Engineering & Technology, Patiala, Punjab, India

    Sandeep Kumar, Arun Kumar Chatterjee & Rishikesh Pandey

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  1. Sandeep Kumar
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  2. Arun Kumar Chatterjee
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  3. Rishikesh Pandey
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Correspondence to Sandeep Kumar, Arun Kumar Chatterjee or Rishikesh Pandey.

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Kumar, S., Chatterjee, A.K. & Pandey, R. Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET. Silicon 13, 3447–3459 (2021). https://doi.org/10.1007/s12633-020-00774-x

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