Skip to main content
SpringerLink
Log in

Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

Deep trench LDMOS is widely used in high-voltage level power devices. This paper proposes and optimizes a deep trench super-junction LDMOS with triangular charge compensation layer (TCCL DT SJ LDMOS), which solves the problem of charge imbalance in the super-junction region due to the Silicon-Insulator-Silicon (SIS) capacitance at both ends of the trench and improves the Breakdown Voltage (BV) of the device. This structure also helps to deplete the drift region at the bottom of the deep trench by adding P-buffer under the N-Pillars, which improves the doping concentration and reduces the specific on-resistance of the device. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the TCCL DT SJ LDMOS has been increased from 498V to 730V, and the power figure of merit (FOM) has increased by 12.8 MW / cm2(FOM = BV2 / Ron, sp).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Coe DJ (1988) High voltage semiconductor device [P]. U.S. Patent 4 754 310

  2. Chen XB (1993) Semiconductor power devices with alternating conductivity type high voltage breakdown region [P]. U.S. Patent 5 216 275

  3. Olujide Adenekan P, Holland K, Kalna (2018) Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications. Microelectron J 81:94–100

  4. Yi B, Chen X (2016) A 300-V ultra-low-specific on-resistance high-side p-LDMOS with auto-biased n-LDMOS for SPIC. IEEE Trans Power Electron 32(1):551–560

  5. Williams RK, Darwish MN, Blanchard RA, Siemieniec R, Rutter P, Kawaguchi Y (2017) The trench power MOSFET: Part I—history, technology, and prospects. IEEE Trans Electron Devices 64(3):674–691

    Article  Google Scholar 

  6. Jiang Q, Wang M, Chen X (2010) A high-speed deep-trench MOSFET with a self-biased split gate. IEEE Trans Electron Devices 57(8):1972–1977

  7. Cheng J, Chen W, Li P (2018) Improvement of deep-trench LDMOS with variation vertical doping for charge-balance super-junction. IEEE Trans Electron Devices 65(4):1404–1410

    Article  CAS  Google Scholar 

  8. Cheng K, Li P, Chen W, Yi B, Chen XB (2018) Simulation study of a super-junction deep-trench LDMOS with a trapezoidal trench. IEEE J Electron Devices Soc 6:1091–1096

    Article  CAS  Google Scholar 

  9. Ying-Wang,, Wang YF, Liu YJ, Wang Y (2017) Split gate SOI trench LDMOS with low-resistance channel. Superlattice Microstruct 102:399–406

  10. Zhou K, Luo X, Li Z, Zhang B (2015) Analytical model and new structure of the variable- k dielectric trench LDMOS with improved breakdown voltage and specific ON-resistance. IEEE Trans Electron Devices 62(10):3334–3340

    Article  CAS  Google Scholar 

  11. Dong Yang S, Lei HJ, Huang Y, Yuan Q, Jiang Y, Guo J, Cheng K, Lin Z, Zhou X, Tang F (2017) An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars. Superlattice Microstruct 112:269–278

  12. Kun Cheng S, Yuan HJianmeiLQi, Jiang Y, Huang Y, Yang D, Lin Z, Zhou X, Tang F (2017) A novel trench SOI LDMOS with a dual floating vertical field plate. Superlattice Microstruct 109:134–144

  13. Mehrad M (2016) Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage. Superlattice Microstruct 91:193–200

  14. Wang Y, Hu HF, Jiao WL (2010) High-performance gate-enhanced power UMOSFET with optimized structure. IEEE Electron Device Lett 31(11):5560725–5561116

    Google Scholar 

  15. Laermer F, Franssila S, Sainiemi L, Kolari K (2010) Deep reactive ion etching. In: Lindroos V, Tilli M, Lehto A, Motooka T (eds) Handbook of Silicon Based MEMS Materials and Technologies. Elsevier, Amsterdam, pp 349–374

    Chapter  Google Scholar 

  16. Zhaozhao Xu D, Liu J, Jin HF, Yang X, Duan W, Yue W, Fang Z, Qian W, Kong W, Shichang Zou (2019) Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS. Microelectron J 88:29–36

  17. Wu L, Huang Y, Wu Y, Zhu L, Lei B (2019) Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation. Mater Sci Semicond Process 101:272–278

    Article  CAS  Google Scholar 

Download references

Acknowledgements

This work was supported by Scientific Research Fund of Hunan Provincial Education Department (No. 19K001).

Author information

Authors and Affiliations

  1. Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics & Electronic Science, Changsha University of Science & Technology, Changsha, 410114, China

    Lijuan Wu, Qilin Ding & Jiaqi Chen

Authors
  1. Lijuan Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Qilin Ding
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jiaqi Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lijuan Wu.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wu, L., Ding, Q. & Chen, J. Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor. Silicon 13, 3441–3446 (2021). https://doi.org/10.1007/s12633-020-00771-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00771-0

Keywords

Search

Navigation