Abstract
In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VTH compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations.
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Panchore, M., Cecil, K. & Singh, J. Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells. Silicon 13, 4527–4533 (2021). https://doi.org/10.1007/s12633-020-00747-0
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DOI: https://doi.org/10.1007/s12633-020-00747-0