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Improvement of Electrical Characteristics of SiGe Source Based Tunnel FET Device

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Abstract

Tunnel Field Effect Transistor (TFET) is one of the most promising alternative device for semiconductor technology and shows better performance as compared to the conventional MOS device in terms of subthreshold swing, OFF current, etc. In this paper, SiGe source-based Heterojunction Tunnel FET has been investigated to enhance the performance of the device in terms of ON current and ION/IOFF ratio. The use of spacers has also been studied for enhancing the drain current. The combination of low-k (SiO2) and a high-k (HfO2) hetero dielectric material have been studied for the use of gate dielectric material as well as at the buried oxide layer. The proposed device offers an ON current of 0.537 mA/μm and an OFF current of 14.4 fA/μm, with an excellent ION/IOFF ratio of 3.72 × 1010. The average subthreshold swing of 28.57 mV/decade has also been achieved, which makes the device steeper. The ambipolar currents have been suppressed and hence the electrical characteristics of the proposed device are improved. The validity of the proposed device has been done by using TCAD simulation tool.

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References

  1. Kahng D (1976) A historical perspective on the development of MOS transistors and related devices. IEEE Trans Electron Devices 23:655–657

    Article  Google Scholar 

  2. Haensch W, Nowak EJ, Dennard RH, Solomon PM, Bryant A, Dokumaci OH, Kumar A, Wang X, Johnson JB, Fischetti MV (2006) Silicon CMOS devices beyond scaling. IBM J Res Dev 50:339–361

    Article  CAS  Google Scholar 

  3. Taylor MB (2012) Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In: DAC Design Automation Conference 2012, IEEE, pp 1131–1136

  4. Bohr M (2007) A 30 year retrospective on Dennard's MOSFET scaling paper. IEEE Solid-State Circuits Society Newsletter 12:11–13

    Article  Google Scholar 

  5. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329

    Article  CAS  Google Scholar 

  6. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–2110

    Article  CAS  Google Scholar 

  7. Sinha SK, Chaudhury S (2013) Impact of oxide thickness on gate capacitance-- a comprehensive analysis on MOSFET, nanowire FET and CNTFET devices. IEEE Trans Nanotechnol 12:958–964

    Article  CAS  Google Scholar 

  8. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-ĸ gate dielectric. IEEE Trans Electron Devices 54:1725–1733

    Article  CAS  Google Scholar 

  9. Yu-chen L et al (2014) Double-gate tunnel field-effect transistor: gate threshold voltage modeling and extraction. J Cent South Univ 21(2):587–592

    Article  Google Scholar 

  10. Toh EH, Wang GH, Samudra G, Yeo YC (2007) Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Appl Phys Lett 90:263507

    Article  Google Scholar 

  11. Nagavarapu V, Jhaveri R, Woo JC (2008) The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans Electron Devices 55:1013–1019

    Article  CAS  Google Scholar 

  12. Vandana DW, Bhowmick B (2019) Optimisation of pocket doped junctionless TFET and its application in digital inverter. Micro Nano Lett 14:69–73

    Article  Google Scholar 

  13. Abdi DB, Kumar MJ (2014) In-built N+ pocket pnpn tunnel field-effect transistor. IEEE Electron Device Lett 35:1170–1172

    Article  CAS  Google Scholar 

  14. Das GD, Mishra GP, Dash S (2018) Impact of source-pocket engineering on device performance of dielectric modulated tunnel FET. Superlattice Microst 124:131–138

    Article  CAS  Google Scholar 

  15. Singh PK, Baral K, Kumar S, Chander S, Tripathy MR, Singh AK, Jit S (2020) Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis. Appl Phys A 126:166

    Article  CAS  Google Scholar 

  16. Sinha SK, Chaudhury S (2015) Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET. Mater Sci Semicond Process, Elsevier 31:431–438

  17. Yeo YC, Han G, Yang Y, Guo P (2010) Strain engineering and junction design for tunnel field-effect transistor. ECS Trans 33:77–87

    Article  CAS  Google Scholar 

  18. Wang L, Yu E, Taur Y, Asbeck P (2010) Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications. IEEE Electron Device Lett 31:431–433

    Article  CAS  Google Scholar 

  19. Kumar S, Singh K, Chander S, Goel E, Singh PK, Baral K, Singh B, Jit S (2017) 2-D analytical drain current model of double-gate heterojunction TFETs with a SiO 2/HfO 2 stacked gate-oxide structure. IEEE Trans Electron Devices 65:331–338

    Article  Google Scholar 

  20. Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Trans Electron Devices 58:677–683

    Article  CAS  Google Scholar 

  21. Singh B, Rai TN, Gola D, Singh K, Goel E, Kumar S, Tiwari PK, Jit S (2017) Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: a superior structure. Mater Sci Semicond Process 71:161–165

    Article  CAS  Google Scholar 

  22. Li C, Yan ZR, Zhuang YQ, Zhao XL, Guo JM (2018) Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric. Chin Phys B 27(7):078502

    Article  Google Scholar 

  23. Dubey PK, Kaushik BK (2017) T-shaped III-V heterojunction tunneling field-effect transistor. IEEE Trans Electron Devices 64:3120–3125

    Article  CAS  Google Scholar 

  24. Chander S, Baishya S, Sinha S, Kumar S, Singh P, Baral K, Tripathy M, Singh A, Jit S (2019) Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs. Superlattice Microst 131:30–39

    Article  CAS  Google Scholar 

  25. Choi WY, Lee HK (2016) Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Nano Converg 3(13):1–15

    CAS  Google Scholar 

  26. Schlosser M, Bhuwalka KK, Sauter M, Zilbauer T, Sulima T, Eisele I (2008) Fringing-induced drain current improvement in the tunnel field-effect transistor with high-k and gate dielectrics. IEEE Trans Electron Devices 56:100–108

    Article  Google Scholar 

  27. Baruah RK, Paily RP (2013) Impact of high-k spacer on device performance of a junctionless transistor. J Comput Electron 12:14–19

    Article  CAS  Google Scholar 

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Authors and Affiliations

  1. School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

    Irfan Ahmad Pindoo, Sanjeet Kumar Sinha & Sweta Chander

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  1. Irfan Ahmad Pindoo
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  2. Sanjeet Kumar Sinha
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  3. Sweta Chander
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Correspondence to Sanjeet Kumar Sinha.

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Pindoo, I.A., Sinha, S.K. & Chander, S. Improvement of Electrical Characteristics of SiGe Source Based Tunnel FET Device. Silicon 13, 3209–3215 (2021). https://doi.org/10.1007/s12633-020-00674-0

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  • DOI: https://doi.org/10.1007/s12633-020-00674-0

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