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Investigation of Temperature Variation and Interface Trap Charges in Dual MOSCAP TFET

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Abstract

This work performs the investigation of Dual MOS-Capacitor (D-MOS) TFET having a δ-Doped architecture. Three different structural variations are studied and it is found that the proposed device outperforms the other two in terms of average subthreshold swing (SSavg) and ION/IOFF ratio. The proposed device possesses an SSavg of 18.67 mV/dec and ION/IOFF ratio of 5.67 × 108. Further examination has been performed by considering wide range of temperature and it is observed that the proposed device characteristics is less affected by temperature variations. Also, the effect of both uniform and Gaussian type of interface traps are considered in this work. The degradation of Gaussian traps is more prominent in comparison with the uniform trap but the results still shows quite better ION/IOFF (105). Hence, the proposed device can be used as a comparatively reliable low power device.

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Acknowledgements

This Publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation (formerly Media Lab Asia).

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, 788010, India

    Vandana Devi Wangkheirakpam, Brinda Bhowmick & Puspa Devi Pukhrambam

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  1. Vandana Devi Wangkheirakpam
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  2. Brinda Bhowmick
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  3. Puspa Devi Pukhrambam
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Correspondence to Vandana Devi Wangkheirakpam.

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Wangkheirakpam, V.D., Bhowmick, B. & Pukhrambam, P.D. Investigation of Temperature Variation and Interface Trap Charges in Dual MOSCAP TFET. Silicon 13, 2971–2978 (2021). https://doi.org/10.1007/s12633-020-00651-7

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  • DOI: https://doi.org/10.1007/s12633-020-00651-7

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