Abstract
In this study, an analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation. The threshold voltage with channel length 50 nm was compared with the published experimental results achieved from tri-gate FinFET. Separate solutions of 2D Poisson’s equation were obtained for both symmetric and asymmetric double gate FinFET and combined using the perimeter-weighted sum approach to achieve the surface potential for TG-FinFET. The inversion charge model was used to find the threshold voltage of the above mentioned device. The results of the model were obtained for different channel lengths, fin widths and fin heights on the silicon substrate. A comparative study of hafnium dioxide (HfO2) and silicon dioxide (SiO2) for the same oxide thickness was delineated to depict the influence of the high dielectric material on the model of FinFET. As anticipated, the oxide thickness of HfO2 is greater than SiO2 to maintain the same surface potential. The result of the analytical model was well agreed with the TCAD simulation outcome. Hence, it can be considered as a promising model in device technology.
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References
Dennard R, Gaensslen F, Yu H, Rideout V, Bassous E, LeBlanc A (1974) Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J Solid State Circuits 9:256–268
Razavieh A., Zeitzoff, P., Brown, E. D., Karve, G., . Nowak, J E: ‘Scaling challenges of FinFET architecture below 40 nm contacted gate pitch’, in Proc DRC Proc, 2017, pp. 231–232
Dennard, R., Gaensslen, F., Kuhn, L., Yu, H.: ‘Design of micron MOS switching devices’, IEEE IEDM Tech Dig, 1972, pp. 168–170
Lo S, Buchanan D, Taur Y, Wang W (1997) Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide n MOSFET’s. IEEE Electron Device Lett 18:209–212
Maity NP, Maity R, Baishya S (2017) Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices. Superlattice Microst 111:628–641
Maity NP, Maity R, Thapa RK, Baishya S (2016) A tunneling current density model for ultra-thin HfO2 high-k dielectric material based MOS devices. Superlattice Microst 95:24–32
Poiroux T, Vinet M, Faynot O, Widiez J, Lolivier J, Previtali B, Ernst T, Deleonibus S (2006) Multigate silicon MOSFETs for 45 nm node and beyond. Solid State Electron 50(1):18–23
Maity NP, Maity R, Maity S, Baishya S (2019) Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation. J Comput Electron 18:492–499
Chakraborti H, Maity R, Maity NP (2019) Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation. Microsyst Technol 25:4675–4684
Maity NP, Maity R, Baishya S (2018) A tunneling current model with practical barrier for ultra thin high-k dielectric ZrO2 material based MOS devices. Silicon 10:1645–1652
Hu SG, Hao Y, Ma XH et al (2009) Condensed matter: electronic structure, Electrical, Magnetic and Optical properties: Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature. Chin Phys B 18(12):5479–5484
Papathanasiou K, Theodorou GC, Tsormpatzoglou A et al (2012) Symmetrical unified compact model of short-channel double-gate MOSFETs. Solid State Electron 69:55–61
Frank, J D., Lau, E S., Fischetti, VM.: ‘Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?’, IEEE IEDM Tech Dig, 1992, pp. 553–556
Wong, P.S H., Frank, JD, Salomon, M P: ‘Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation’, IEEE IEDM Tech Dig, 1998, pp. 98–101
Loubet, N., Hook, T., Montanini, et al: ‘Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET’, in Proc VLSI Symp Dig, 2017, pp. T230–T231
Breil, N., Carr, A., Kuratomi, T., et al.: ‘Highly-selective super conformal CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures,’ in Proc. VLSI Symp Dig, 2017, pp. T216–T217
Razavieh A, Zeitzoff P, Nowak JE (2019) Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans Nanotechnol 18:999–1004
Maity NP, Maity R, Baishya S (2019) An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J Comput Electron 18(1):65–75
Hong Y, Guo Y, Yang H et al (2014) A novel bulk FinFET with dual-material gate. IEEE Int. Conf. Solid-State and Integrated Circuit Technology, Guilin
Colinge PJ (2004) Multiple-gate MOSFETs. Solid State Electron 48(6):897–905
Collaert N, de Keersgieter A et al (2005) Performance improvement of tall triple gate devices with strained SiN layers. IEEE Electron Device Lett 26:820–822
Doyle SB, Datta S, Doczy M et al (2003) High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett. 24:263–265
Park TJ, Colinge PJ (2002) Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans Electron Devices 49(12):2222–2229
Frank JD, Taur Y, Wong SH (1998) Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Device Lett 19(10):385–387
Yang WJ, Fossum GJ (2005) On the feasibility of nanoscale triple gate CMOS transistors. IEEE Trans Electron Devices 52(6):1159–1164
Riddit C, Alexander C, Brown et al (2011) Simulation of “Ab Initio” Quantum Confinement Scattering in UTB MOSFETs Using Three-Dimensional Ensemble Monte Carlo. IEEE Trans Electron Devices 58(3):600–608
Jin Y, Zeng C, Ma L, Barlage D (2007) Analytical threshold voltage model with TCAD simulation verification for design and evaluation of tri-gate MOSFETs. Solid-Sate Electron 51(3):347–353
Kloes A, Goebel D, Bosworth BT (2008) Three-dimensional closed-form model for potential barrier in undoped FinFETs resulting in analytical equations for VT and subthreshold slope. IEEE Trans Electron Dev 55(12):3467–3475
Kolberg S, Fjeldly T (2006) A.: ‘2D modelling of nanoscale double gate silicon-on insulator MOSFETs using conformal mapping’. Phys Scr T126:57–60
Tsormpatzoglou A, Dimitriadis CA, Clerc R, Rafhay Q, Pananakakis G, Ghibaudo G (2007) Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs. IEEE Trans Electron Devices 54(8):1943–1952
Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices 36(2):399–402
Auth CP, Plummer JD (1998) A simple model for threshold voltage of surrounding-gate MOSFETs. IEEE Trans Electron Devices 45(11):2381–2383
Ma Y, Li Z, Tian L, Yu Z (2000) Effective density-of-states approach to QM correction in MOS structures. Solid State Electron 44(3):401–407
Pei G, Kedzierski J, Oldiges P, Ieong M, Kan ECC (2002) FinFET design consideration based on 3-D simulation and analytical modeling. IEEE Trans Electron Dev 49(8):1411–1419
Tsormpatzoglou A, Tassis HD, Dimitriadis AC et al (2011) Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs. Solid State Electron 57(1):31–34
Chakrabarti H, Maity R, Baishya S, Maity NP (2020) An accurate model for threshold voltage analysis of dual material double gate metal oxide semiconductor field effect transistor. Silicon. https://doi.org/10.1007/s12633-020-00553-8
Maity NP, Maity R, Dutta S, Deb S, Rao KS, Sravani G, Baishya S (2020) Effects of hafnium oxide on surface potential and drain current models for subthreshold short channel metal–oxide–semiconductor-field-effect-transistor. Transactions on Electrical and Electronics Materials. https://doi.org/10.1007/s42341-020-00181-4
Maity NP, Maity R, Thapa RK, Baishya S (2014) Study of interface charge densities for ZrO2 and HfO2 based metal-oxide semiconductor devices. Advances in Material Science & Engineering 2014(Article ID 497274):1–6
Tsormpatzoglou A, Dimitriadis CA, Clerc R et al (2008) Semi analytical modeling of short-channel effects in lightly doped silicon, tri-gate MOSFETs. IEEE Trans Electron Dev 55(10):2623–2631
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The authors would like to thank and highly indebted to TCAD Laboratory, National Institute of Technology, Silchar, India for supporting this technical work.
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Panchanan, S., Maity, R., Baishya, S. et al. Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET. Silicon 13, 3271–3289 (2021). https://doi.org/10.1007/s12633-020-00607-x
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DOI: https://doi.org/10.1007/s12633-020-00607-x