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Extensive Study of Underlap Length Effect for 3-D SOI FinFET to Achieve High Switching Ratio and Low Power

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Abstract

The primary purpose of this work is to study the effect of symmetric and asymmetric variation of underlap regions both on source and drain side of 3D SOI n-FinFET. Underlap length is proved to be a critical parameter of FinFET in deciding the leakage current (Ioff) and the performance of the device in addition to other important parameters like Fin height (HFin), Fin width (WFin) and Aspect ratio (HFin/WFin). The physical parameters considered in this work are symmetric underlap length (Lun), source side underlap length (Lus) and drain side underlap length (Lud). The simulation result shows that Lud variation has greater effect on Ion/Ioff as compared to Lus and Lun variation, while the later two variation has similar effect on the switching ratio. At 15 nm (0.75 × Lg) of Lud, FinFETs appreciably allows a sufficient on current (Ion), highest Ion/Ioff while maintaining low leakage current. Moreover, it is observed that for optimum values of Lus and Lud, the Ion / Ioff ratio shifted from 1.55 × 106 to 2.12 × 106 which is about 36% improvement as compared to the existing device. However, a minimal enhancement in the subthreshold swing is reported i.e., from 65 mV/decade to 64 mV/decade. These parameters are obtained for an appropriate choice of Lus = 10 nm (0.5 × Lg) and Lud = 15 nm (0.75 × Lg).

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References

  1. Critchlow DL (1999) MOSFET scaling-the driver of VLSI technology. Proc IEEE 87(4):659–667

    Article  Google Scholar 

  2. Critchlow DL (2007) Recollections on MOSFET scaling. IEEE Solid-State Circuits Soc Newsletter 12(1):19–22

    Article  Google Scholar 

  3. Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (1974) Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J Solid State Circuits 9(5):256–268

    Article  Google Scholar 

  4. Davari B, Dennard RH, Shahidi GG (1995) CMOS scaling for high performance and low power-the next ten years. Proc IEEE 83(4):595–606

    Article  Google Scholar 

  5. V. K. Khanna (2016) Short-channel effects in MOSFETs, in Integrated Nanoelectronics, Springer, pp. 73–93

  6. D’Agostino F, Quercia D (2000) Short-channel effects in MOSFETs. Introd to VLSI Des (EECS 467) 70:71–72

    Google Scholar 

  7. Iwai H (2009) Roadmap for 22 nm and beyond. Microelectron Eng 86(7–9):1520–1528

    Article  CAS  Google Scholar 

  8. Colinge JP (2008) The new generation of SOI MOSFETs. Rom J Inf Sci Techno 11(1):3–15

    Google Scholar 

  9. Thompson SE, Parthasarathy S (2006) Moore’s law: the future of Si microelectronics. Mater Today 9(6):20–25

    Article  CAS  Google Scholar 

  10. Moore GE et al (1965) Cramming more components onto integrated circuits. McGraw-Hill, New York

    Google Scholar 

  11. Skotnicki T, Hutchby JA, King T-J, Wong H-S, Boeuf F (2005) The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits Devices Mag 21(1):16–26

    Article  Google Scholar 

  12. K. J. Kuhn, M. Y. Liu, and H. Kennel (2010) Technology options for 22nm and beyond, in 2010 International Workshop on Junction Technology Extended Abstracts, pp. 1–6

  13. C. Dančak (2018) The FinFET: A Tutorial, in Semiconductor Nanotechnology, Springer, pp. 37–69

  14. M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann, and S. Biesemans (2009) Review of FINFET technology, in 2009 IEEE international SOI conference, pp. 1–4

  15. Crupi F, Alioto M, Franco J, Magnone P, Togo M, Horiguchi N, Groeseneken G (2012) Understanding the basic advantages of bulk FinFETs for sub-and near-threshold logic circuits from device measurements. IEEE Trans Circuits Syst Express Briefs 59(7):439–442

    Article  Google Scholar 

  16. B. Yu et al. (2002) FinFET scaling to 10 nm gate length, in Digest. IEEE IEDM, pp. 251–254

  17. Pei G, Kedzierski J, Oldiges P, Ieong M, Kan E-C (2002) FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans Electron Devices 49(8):1411–1419

    Article  Google Scholar 

  18. Mohapatra SK, Pradhan KP, Singh D, Sahu PK (2015) The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: an analysis towards analog and RF circuit design. IEEE Trans Nanotechnol 14(3):546–554

    Article  CAS  Google Scholar 

  19. M. Chi (2012) Challenges in manufacturing FinFET at 20nm node and beyond, Technol. Dev.

  20. Bhole M, Kurude A, Pawar S (2013) FinFET-benefits, drawbacks and challenges. Int J Eng Sci Res Technol 2:3219–3222

    Google Scholar 

  21. Zhao H, Yeo Y-C, Rustagi SC, Samudra GS (2008) Analysis of the effects of fringing electric field on FinFET device performance and structural optimization using 3-D simulation. IEEE Trans Electron Devices 55(5):1177–1184

    Article  CAS  Google Scholar 

  22. Trivedi V, Fossum JG, Chowdhury MM (2004) Nanoscale FinFETs with gate-source/drain underlap. IEEE Trans Electron Devices 52(1):56–62

    Google Scholar 

  23. P. K. Pal, B. K. Kaushik, and S. Dasgupta (2013) Optimization of underlap FinFETs and its SRAM performance projections using high-k spacers, in VLSI Design and Test, Springer, pp. 267–273

  24. Goel A, Gupta SK, Roy K (2010) Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Trans Electron Devices 58(2):296–308

    Article  Google Scholar 

  25. Sachid AB, Chen M-C, Hu C (2016) FinFET with high-$$\$kappa $ spacers for improved drive current. IEEE electron device Lett 37(7):835–838

    Article  CAS  Google Scholar 

  26. A. A. Goud, R. Venkatesan, A. Raghunathan, and K. Roy (2015) Asymmetric underlapped FinFET based robust SRAM design at 7nm node, in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 659–664

  27. de Andrade MGC, Martino JA, Aoulaiche M, Collaert N, Simoen E, Claeys C (2012) Behavior of triple-gate bulk FinFETs with and without DTMOS operation. Solid State Electron 71:63–68

    Article  Google Scholar 

  28. Elgamal M, Sinjab A, Fedawy M, Shaker A (2019) Effect of doping profile and the work function variation on performance of double-gate TFET. Int J Integr Eng 11(7):40–46

    Article  Google Scholar 

  29. Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans Electron Devices 54(12):3308–3316

    Article  CAS  Google Scholar 

  30. Pal PK, Kaushik BK, Dasgupta S (2013) High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs. IEEE Trans Electron Devices 60(10):3371–3377

    Article  CAS  Google Scholar 

  31. Z. Krivokapic et al (2017) 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications, in 2017 IEEE International Electron Devices Meeting (IEDM), pp. 11–15

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Authors and Affiliations

  1. School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India

    Asharani Samal & Sushanta Kumar Mohapatra

  2. Department of Electronics & Communication, Indian Institute of Information Technology Design and Manufacturing (IIITDM), Kancheepuram, Chennai, India

    Kumar Prasannajit Pradhan

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  1. Asharani Samal
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  2. Kumar Prasannajit Pradhan
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  3. Sushanta Kumar Mohapatra
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Correspondence to Kumar Prasannajit Pradhan.

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Samal, A., Pradhan, K.P. & Mohapatra, S.K. Extensive Study of Underlap Length Effect for 3-D SOI FinFET to Achieve High Switching Ratio and Low Power. Silicon 13, 1059–1064 (2021). https://doi.org/10.1007/s12633-020-00495-1

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