Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor


In this paper, five layered Black Phosphorus (BP) – Silicon (Si) based Tunnel Field Effect Transistor (TFET) is used to overcome the thermionic limits faced by Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and analysis of the device validates that TFET is a better alternative as nano scale transistor. To enhance the ON state current for five layered BP-Si based TFET, multi electrode (source and drain) based structure is used. For the first time, the charge plasma technique is implemented on BP. The proper work function of metal electrodes has been selected to accordingly implement the charge plasma based technique for BP and Si. Charge plasma will result in generation of electron and hole cloud depending on the work functions at source/drain electrode. Different device properties and characteristics curves viz. IDS-VGS and IDS-VDS are compared for monolayered TFET to five layered based TFET. Different analog/RF properties, as well as linear and distortion parameters of the device such as output conductance (gd), transconductance (gm), cut-off frequency (fT), third order intermodulation distortion, second and third order harmonic distortion, second and third order voltage intercept point and current intercept point, are examined for five layered BP-Si based TFET only. For five layered BP-Si based configuration, the proposed device offers a threshold voltage of 0.42 V, an average subthreshold slope of 24.14 mV/dec, ION of 1.7 × 10−4 A/μm, Drain Induced Barrier Lowering (DIBL) of 1.02 mV/V.

This is a preview of subscription content, access via your institution.


  1. 1.

    S.O. Koswatta, M.S. Lundstrom, M.S. Nikonov,” D.E. performance comparison between tunneling transistors and conventional MOSFETS”, IEEE TEd, vol. 56, no. 3, pp. 456–465, 2009

  2. 2.

    J.P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhayan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy,” Nanowire Transistors without Junctions”, Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, 2010

  3. 3.

    Bhuwalka KK, Schulze J, Eisele I (2010) Scaling the vertical Tunnel FET with Tunnel bandgap modulation and gate workfunction engineering. IEEE TEd 52(5):909–917

  4. 4.

    Choi WY, Park BG, Lee JD (2007) Tunneling field-effect transistors(TFETs) with subthreshold swing(ss) less than 60 mV/dec. IEEE EDl 28(8):743–745

  5. 5.

    Seabaugh C, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12):2095–2110

    CAS  Article  Google Scholar 

  6. 6.

    A.M. Ionescu, H. Riel,” Tunnel field-effect transistors as energy efficient electronic switches” Nature Publications, vol. 479, pp. 329–337, (2011)

  7. 7.

    Rajasekharan B, Hueting RJE, Salm C, van Hemert T, Wolters RAM, Schmitz J (2010) Fabrication and characterization of the charge-plasma diode. IEEE EDl 31(6):528–530

  8. 8.

    Sunny A, Intekhab Amin S, Sarin RK (2016) Analog performance investigation of dual electrode based doping-less tunnel FET. JCE 15(1):94–103

  9. 9.

    Jagadesh Kumar M (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE TEd 60(10):3285–3290

  10. 10.

    Sunny A, Sarin RK (2016) An analysis on ambipolar reduction techniques for charge plasma based tunnel FETs. Journal of Nanoelectronics and Optpelectronics 11(4):543–550

    Article  Google Scholar 

  11. 11.

    Kumar N, Raman A (2019) Design and Investigation of Charge-Plasma Based Work Function Engineered DualMetal-Heterogeneous Gate Si-Si0.55Ge0.45 GAA-Cylindrical NWTFET for Ambipolar Analysis. IEEE TEd 66

  12. 12.

    Kumar P, Gupta M, Singh K (2019) Performance Evaluation of Transition Metal Dichalcogenides Based Steep Subthrehold Slope Tunnel Field Effect Transistor. Silicon

  13. 13.

    Roy T, Tosun M, Cao X, Fang H, Lien DH, Zhao P, Chen YZ, Chueh YL, Guo J (2015) A. Javey “dual-gated MoS2/WSe2 Van Der Waals tunnel diodes and transistors”. ACS Nano 9:207–2079

  14. 14.

    Yan R, Fathipour S, Han Y, Song B, Xiao S, Li M, Protasenko V, Muller DA, Jena D, Xing HG (2015) Diodes in Van Der Waals Heterojunctions with Broken-Gap Energy Band Alignment. Nano Lett. 15:5791–5798

    CAS  Article  Google Scholar 

  15. 15.

    Roy T, Tosun M, Hettick M, Ahn GH, Javey A (2016) 2D-2D Tunneling Field-Effect Transistors Using WSe2/SnSe2 Heterostructures. Appl. Phys. Lett. 108(08)

  16. 16.

    Qiao J, Kong X, Hu Z-X (2014) Few layered black Phosphorus: emerging 2D semiconductor with high anisotropic carrier mobility and linear dichroism. Nat. Commun. 5:4475

    CAS  Article  Google Scholar 

  17. 17.

    Luisier M, Klimeck G (2010) Simulation of nanowire tunneling transistors: from the WentzeleKramerseBrillouin approximation to full-band phonon assisted tunnelling. J. Appl. Phys. 107(08)

  18. 18.

    Sze SM, Kwok KN (2007) Physics of Semiconductor Devices, 3rd edition. Wiley Press, New York

    Google Scholar 

  19. 19.

    Knoch J, Mantl S, Appenzeller J (2007) Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid State Electron. 51:572–578

    CAS  Article  Google Scholar 

  20. 20.

    Chiu F-C, Lin S-A, Lee J Y-m (2005) Electrical properties of metal–HfO2–Si system measured from metal–insulator–semiconductor capacitors and metal–insulator–semiconductor field–effect transistors using HfO2 gate dielectric. Elsevier Microelectronics Reliability 45:961–964

    CAS  Article  Google Scholar 

  21. 21.

    Hubbard KJ, Schlom DG (1996) Thermodynamic stability of binary oxides in contact with Si. J Mater Res 11(11):2757–2776

    CAS  Article  Google Scholar 

  22. 22.

    ATLAS (2012) Device simulation software. Silvaco Int, Santa Clara

    Google Scholar 

  23. 23.

    Peng Wu, Tarak Ameen, Huairuo Zhang, Leonid A. Bendersky, Hesameddin Latikhameneh, Gerhard Klimeck, Rajib Rahman, Albert V. Davvydov and Joerg Appenzeller,” Complementry Black Phosphorus Tunneling Field-Effect transistors” ACS Nano, 2018. Supplementry file:

  24. 24.

    Gurmeet Singh, S Intekhab Amin, Sunny Anand, R.K. Sarin,” Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation”, Superlattice Microst, vol. 92, pp. 143–156, 2016

  25. 25.

    Kumar N, Mushtaq U, Amin SI, Anand S (2019) Design and performance analysis of dual gate all around core shell nanotube TFET. Superlattice Microst 125:356–364

    CAS  Article  Google Scholar 

  26. 26.

    Anand S, Sarin RK (2017) Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance. Journal of Semiconductors 38

  27. 27.

    Kumar N, Raman A (2019) Low voltage charge-plasma based dopingless tunnel field effect transistor: analysis and optimization. Microsyst Technol:1–8

  28. 28.

    Ehsanur Rahman, Abir Shadman, Imtiaz Ahmed, Saeed Uz Zaman Khan, Quazi D M Khosru (2018) A physically based compact I-V model for monolayer TMDC channel MOSFET and DMFET biosensor, nanotechnology, IOP publishing

  29. 29.

    Prabhat Kumar Dubey, Brajesh Kumar Kaushik” A charge plasma-based monolayer transition metal dichalcogenide tunnel FET” IEEE TEd, vol. 66, 2019

  30. 30.

    Chaujar R, Kaur R, Saxena M, Gupta M, Gupta RS (2009) TCAD assessment of gate electrode Workfunction engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layereded gate architecture, part II: analog and large signal performance evaluation. Superlattices Microstructure 46(4):645–655

    CAS  Article  Google Scholar 

  31. 31.

    Gupta N, Chaujar R (2016) Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance ofgate stack (gs)-gewe-sinw mosfet. Superlattices Microstructure 97:630–641

    CAS  Article  Google Scholar 

Download references

Author information



Corresponding author

Correspondence to Maneesha Gupta.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Kumar, P., Gupta, M. & Singh, K. Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor. Silicon 12, 2809–2817 (2020).

Download citation


  • Analog parameters
  • Black phosphorous
  • Charge plasma
  • Distortion
  • Linearity
  • TFET