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10 nm TriGate High k Underlap FinFETs: Scaling Effects and Analog Performance

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Abstract

Nano scale devices with improved performance than the conventional CMOS devices is of great need in recent days. The paper investigates the performance of 10 nm Trigate FinFET structure with high k dielectric spacer on either side of the channel in the underlap region. The proposed structure increases the On-Off ratio (ION/ IOFF) of drain current by order of 106 and also improves the subthreshold swing (SS). Further, it enhances the transconductance (gm) at the low gate voltage, raises the output conductance (gd) and intrinsic gain (gm/gd) proving that the device provides efficient analog performance suitable for RF applications.

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Acknowledgements

The authors gratefully acknowledge the support by Centre for Material Science and Nano devices, Dept of Physics & Nanotechnology, Faculty of Engineering and Technology, SRM Institute of Science and Technology, Chennai, India.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Chennai, India

    J. K. Kasthuri Bha & P. Aruna Priya

  2. Centre for Material Science and Nano Devices, Department of Physics and Nanotechnology, SRM Institute of Science and Technology, Chennai, India

    H. Bijo Joseph & D. John Thiruvadigal

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  1. J. K. Kasthuri Bha
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  2. P. Aruna Priya
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  3. H. Bijo Joseph
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  4. D. John Thiruvadigal
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Correspondence to P. Aruna Priya.

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Bha, J.K.K., Priya, P.A., Joseph, H.B. et al. 10 nm TriGate High k Underlap FinFETs: Scaling Effects and Analog Performance. Silicon 12, 2111–2119 (2020). https://doi.org/10.1007/s12633-019-00299-y

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