Abstract
In nanometer regime, the variations in process parameters and environment parameters are increased radically which motivate the use of Statistical Static Timing Analysis (SSTA). In this paper, we propose a process and environment sensitivity based, SSTA algorithm for high speed CMOS technology combinational circuits. The algorithm calculates the propagation delay of the combinational circuits more correctly by considering all process parameters like length, width oxide thickness and dopant of the MOSFET and environment parameters like operating temperature and the supply voltage. To investigate the SSTA analyzer a combinational circuit application is used, namely four bit adder. The designed SSTA algorithm used more correct path based analysis instead of block base analysis. The accuracy of the model is verified using Monte Carlo analysis for 32 nm technology. The proposed SSTA method shows that the average errors 1.43% and 5.98% in mean and standard deviation, respectively compared with Monte Carlo analysis and need less simulation time than Monte Carlo analysis.
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Patil, S.R., Gautam, D.K. Statistical Modeling of Combinational Circuits Using Path Based Delay Analysis. Silicon 10, 2063–2069 (2018). https://doi.org/10.1007/s12633-017-9721-z
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DOI: https://doi.org/10.1007/s12633-017-9721-z