Abstract
Process parameter variations of MOSFET and environment parameter variations of the high speed VLSI circuits have become a critical issue in timing analysis. This paper proposes the statistical modeling of basic logic gates and flip-flops used for combinational logic and sequential logic circuits. The basic logic gates and flip-flops model are developed for 32 nm technology. To analyze the accurate performance of the models, we propose for the first time the model which considers both the process and environment parameter variations. The performance parameters of logic gates, such as propagation delay of logic gates and clock to Q delay time, setup time, and hold time for latches and flip-flops are verified with Monte Carlo analysis. The performance of the circuit depends on the propagation delay of logic gates and flip-flops so we propose our models to calculate the accurate performance of the high speed digital circuits. The model shows better accuracy and takes less time than Monte Carlo analysis to produce results. Finally, it is shown that the models can accurately predict all the timing parameters of logic gates and flip-flops.
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References
Satish KY, Li J, Talarico C, Wang J (2005) A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching. IEEE Computer Society
Xiong J, Tam K, HeE L (2005) Buffer insertion considering process variation. IEEE Computer Society
Tang Q, Rodriguez J, Zjajo A, Berkelaar M (2014) Statistical transistor-level timing analysis using a direct random differential equation solver. IEEE Trans Comput Aided Des Integr Circuits Syst 33(2):210–223
Tang Q, Zjajo A, Berkelaar M, Van der Meijs N (2012) Transistor-level gate model based statistical timing analysis considering correlations. In: Design, automation &, test in Europe conference & exhibition, pp 917–922
Li X, Le J, Celik M, Pileggi LT (2008) Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations. IEEE Trans Comput Aided Des Integr Circuits Syst 27(6):1041–1054
Neiroukh O, Song X (2005) Improving the Process-Variation tolerance of digital circuits using gate sizing and statistical techniques. In: IEEE computer society proceedings of the design automation and test in europe conference and exhibition
Patil SR, Gautam DK (2016) Statistical drain current and input capacitance of MOSFET model for high speed CMOS circuits application. Silicon 8(1):25–31
Morshed TH et al. (2011) BSIM4V4.7 MOSFET Mode -User’s Manual. 2011 UC Berkeley
Jaffari J, Anis M (2008) Statistical thermal profile considering process variations: analysis and applications. IEEE Trans Comput Aided Des Integr Circuits Syst 27(6):1027–1040
Bol D, Ambroise R, Flandre D, Legat J-D (2009) Interests and limitations of technology scaling for subthreshold logic. IEEE Trans Very Large Scale Integr VLSI Syst 17(10):1508–1519
Sean X, Ramalingam SA, Wang D, Pan DZ (2008) Latch modeling for statistical timing analysis. EDAA
International technology road map for semiconductors 2011 Edition
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Patil, S.R., Gautam, D.K. Statistical Modeling of Logic Gates and Flip-Flops for High Speed CMOS Circuits Applications. Silicon 9, 371–378 (2017). https://doi.org/10.1007/s12633-016-9453-5
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DOI: https://doi.org/10.1007/s12633-016-9453-5